mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
|
//
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
// you may not use this file except in compliance with the License.
|
|
// You may obtain a copy of the License at
|
|
//
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
//
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
// See the License for the specific language governing permissions and
|
|
// limitations under the License.
|
|
|
|
#include <stdio.h>
|
|
#include <string.h>
|
|
#include <stdlib.h>
|
|
#include "sdkconfig.h"
|
|
#include "esp_attr.h"
|
|
#include "esp_err.h"
|
|
#include "esp_log.h"
|
|
#include "esp32s2/clk.h"
|
|
#include "esp32s2/ulp.h"
|
|
#include "esp32s2/ulp_riscv.h"
|
|
#include "soc/soc.h"
|
|
#include "soc/rtc.h"
|
|
#include "soc/rtc_cntl_reg.h"
|
|
#include "soc/sens_reg.h"
|
|
#include "ulp_private.h"
|
|
#include "esp_rom_sys.h"
|
|
|
|
esp_err_t ulp_riscv_run(void)
|
|
{
|
|
/* Reset COCPU when power on. */
|
|
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
|
|
|
|
/* The coprocessor cpu trap signal doesnt have a stable reset value,
|
|
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
|
|
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
|
|
|
|
esp_rom_delay_us(20);
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
|
|
|
|
|
|
/* Disable ULP timer */
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
|
/* wait for at least 1 RTC_SLOW_CLK cycle */
|
|
esp_rom_delay_us(20);
|
|
/* Select RISC-V as the ULP_TIMER trigger target. */
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
|
|
|
|
/* Select ULP-RISC-V to send the DONE signal. */
|
|
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
|
|
|
|
/* start ULP_TIMER */
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
|
|
SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
|
|
esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes)
|
|
{
|
|
if (program_binary == NULL) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
if (program_size_bytes > ULP_RESERVE_MEM) {
|
|
return ESP_ERR_INVALID_SIZE;
|
|
}
|
|
|
|
uint8_t* base = (uint8_t*) RTC_SLOW_MEM;
|
|
|
|
//Start by clearing memory reserved with zeros, this will also will initialize the bss:
|
|
memset(base, 0, ULP_RESERVE_MEM);
|
|
memcpy(base, program_binary, program_size_bytes);
|
|
|
|
return ESP_OK;
|
|
}
|