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38d54b4b62
Need to ensure that the cacheline being written back will not be accessed during the write back process.
133 lines
5.1 KiB
ArmAsm
133 lines
5.1 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_bit_defs.h"
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#include "soc/extmem_reg.h"
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/**
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* @brief Write back the cache items of DCache, enable cache freeze during writeback.
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* Operation will be done CACHE_LINE_SIZE aligned.
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* If the region is not in DCache addr room, nothing will be done.
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* Please do not call this function in your SDK application.
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* @param uint32_t addr: start address to write back
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* @param uint32_t items: cache lines to invalidate, items * cache_line_size should
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* not exceed the bus address size(4MB)
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*
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* void cache_writeback_items_freeze(uint32_t addr, uint32_t items)
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*/
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/*******************************************************************************
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This function is a cache write-back function that works around the following
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hardware errata on the ESP32-S3:
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- Core X manually triggers (via the EXTMEM_DCACHE_SYNC_CTRL_REG register) the
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write-back of one or more cache lines.
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- While the write-back is in progress, there are two scenarios that may cause
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cache hit error.
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- Core X enters the interrupt handler and access the same cache line
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being written back.
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- Core Y access the same cache line being written back.
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To workaround this errata, the following steps must be taken when manually
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triggering a cache write-back:
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- Core X must disable interrupts so that it cannot be preempted
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- Core X must freeze the cache (via the EXTMEM_DCACHE_FREEZE_REG register) to
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prevent Core Y from accessing the same cache lines that are about to be written
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back.
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- Core X now triggers the cache write-back. During the write-back...
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- If Core Y attempts the access any address in the cache region, Core Y will
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busy wait until the cache is unfrozen.
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- Core X must ensure that it does not access any address in the cache region,
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otherwise Core X will busy wait thus causing a deadlock.
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- After the write-back is complete, Core X unfreezes the cache, and reenables
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interrupts.
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Notes:
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- Please do not modify this function, it must strictly follow the current execution
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sequence, otherwise it may cause unexpected errors.
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- This function is written in assmebly to ensure that the function itself never
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accesses any cache address while the cache is frozen. Unexpected cache access
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could occur if...
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- the function triggers an window overflow onto a stack placed in PSRAM.
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Thus, we only use two window panes (a0 to a8) in this function and trigger
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all window overflows before freezing the cache.
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- the function accesses literals/read-only variables placed in Flash.
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*******************************************************************************/
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.align 4
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/*
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Create dedicated literal pool for this function. Mostly used to store out
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of range movi transformations.
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*/
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.literal_position
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.global cache_writeback_items_freeze
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.type cache_writeback_items_freeze, @function
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cache_writeback_items_freeze:
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entry sp, 32
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/* REG_WRITE(EXTMEM_DCACHE_SYNC_ADDR_REG, addr); */
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movi a4, EXTMEM_DCACHE_SYNC_ADDR_REG
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s32i a2, a4, 0
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/* REG_WRITE(EXTMEM_DCACHE_SYNC_SIZE_REG, items); */
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movi a4, EXTMEM_DCACHE_SYNC_SIZE_REG
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s32i a3, a4, 0
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memw /* About to freeze the cache. Ensure all previous memory R/W are completed */
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movi a2, EXTMEM_DCACHE_FREEZE_REG
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movi a3, EXTMEM_DCACHE_SYNC_CTRL_REG
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/*
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REG_CLR_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_MODE);
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REG_SET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_ENA);
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*/
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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movi a5, ~(EXTMEM_DCACHE_FREEZE_MODE_M)
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and a4, a4, a5
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movi a5, EXTMEM_DCACHE_FREEZE_ENA_M
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or a4, a4, a5
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s32i a4, a2, 0 /* *(EXTMEM_DCACHE_FREEZE_REG) = a4 */
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/* while (!REG_GET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_DONE)); */
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movi a5, EXTMEM_DCACHE_FREEZE_DONE_M
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_wait_freeze_done:
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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memw
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bnone a4, a5, _wait_freeze_done
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/* REG_SET_BIT(EXTMEM_DCACHE_SYNC_CTRL_REG, EXTMEM_DCACHE_WRITEBACK_ENA); */
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l32i a4, a3, 0 /* a4 = *(EXTMEM_DCACHE_SYNC_CTRL_REG) */
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movi a5, EXTMEM_DCACHE_WRITEBACK_ENA_M
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or a4, a4, a5
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s32i a4, a3, 0 /* *(EXTMEM_DCACHE_SYNC_CTRL_REG) = a4 */
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/* while(!REG_GET_BIT(EXTMEM_DCACHE_SYNC_CTRL_REG, EXTMEM_DCACHE_SYNC_DONE)); */
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movi a5, EXTMEM_DCACHE_SYNC_DONE_M
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_wait_writeback_done:
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l32i a4, a3, 0 /* a4 = *(EXTMEM_DCACHE_SYNC_CTRL_REG) */
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memw
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bnone a4, a5, _wait_writeback_done
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/* REG_CLR_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_ENA); */
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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movi a5, ~(EXTMEM_DCACHE_FREEZE_ENA_M)
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and a4, a4, a5
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s32i a4, a2, 0 /* *(EXTMEM_DCACHE_FREEZE_REG) = a4 */
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/* while (REG_GET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_DONE)); */
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movi a5, EXTMEM_DCACHE_FREEZE_DONE_M
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_wait_unfreeze_done:
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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memw
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bany a4, a5, _wait_unfreeze_done
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retw
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.size cache_writeback_items_freeze, . - cache_writeback_items_freeze
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