mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-20 10:46:02 -04:00
2906a25988
This commit separates out the common USB types used throughout most of the stack into its own header file inside the USB component. The types used in the USB HAL are now exclusive to the HAL.
430 lines
18 KiB
C
430 lines
18 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stddef.h>
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#include <stdint.h>
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#include <assert.h>
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#include <string.h>
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#include "hal/usbh_hal.h"
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#include "hal/usbh_ll.h"
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/* -----------------------------------------------------------------------------
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------------------------------- Macros and Types -------------------------------
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----------------------------------------------------------------------------- */
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// -------------------------------- Constants ----------------------------------
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#define BENDPOINTADDRESS_NUM_MSK 0x0F //Endpoint number mask of the bEndpointAddress field of an endpoint descriptor
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#define BENDPOINTADDRESS_DIR_MSK 0x80 //Endpoint direction mask of the bEndpointAddress field of an endpoint descriptor
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#define CORE_REG_GSNPSID 0x4F54400A
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#define CORE_REG_GHWCFG1 0x00000000
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#define CORE_REG_GHWCFG2 0x224DD930
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#define CORE_REG_GHWCFG3 0x00C804B5
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#define CORE_REG_GHWCFG4 0xD3F0A030
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// ------------------------------ Configurable ---------------------------------
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#define CHAN_MAX_SLOTS 16
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/*
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FIFO lengths configured as follows:
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RXFIFO (Receive FIFO)
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- Recommended: (((LPS/4) + 2) * NUM_PACKETS) + (NUM_CHAN * 2) + (NUM_BULK_CTRL * 1)
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- Actual: Assume (LPS = 64), (NUM_CHAN = 8), (NUM_BULK_CTRL = 8):
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NPTXFIFO (Non-periodic TX FIFO)
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- Recommended: (((LPS/4) + 2) * 2) Fit two largest packet sizes (and each packets overhead info)
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- Actual: Assume LPS is 64 (is the MPS for CTRL/BULK/INTR in FS)
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PTXFIFO (Periodic TX FIFO)
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- Recommended: ((LPS/4) + 2) * NUM_PACKETS
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- Actual: Assume a single LPS of 64 (quarter of ISO MPS), then 2 packets worth of overhead
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REGFIFO (Register storage)
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- Recommended: 4 * NUM_CHAN
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- Actual: Assume NUM_CHAN is 8
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*/
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#define HW_FIFO_LEN 256
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#define RX_FIFO_LEN 92
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#define NPTX_FIFO_LEN 36
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#define PTX_FIFO_LEN 72
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#define REG_FIFO_LEN 32
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_Static_assert((RX_FIFO_LEN + NPTX_FIFO_LEN + PTX_FIFO_LEN + REG_FIFO_LEN) <= HW_FIFO_LEN, "Sum of FIFO lengths not equal to HW_FIFO_LEN");
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/**
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* The following core interrupts will be enabled (listed LSB to MSB). Some of these
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* interrupts are enabled later than others.
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* - USB_LL_INTR_CORE_PRTINT
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* - USB_LL_INTR_CORE_HCHINT
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* - USB_LL_INTR_CORE_DISCONNINT
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* The following PORT interrupts cannot be masked, listed LSB to MSB
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* - USBH_LL_INTR_HPRT_PRTCONNDET
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* - USBH_LL_INTR_HPRT_PRTENCHNG
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* - USBH_LL_INTR_HPRT_PRTOVRCURRCHNG
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*/
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#define CORE_INTRS_EN_MSK (USB_LL_INTR_CORE_DISCONNINT)
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//Interrupts that pertain to core events
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#define CORE_EVENTS_INTRS_MSK (USB_LL_INTR_CORE_DISCONNINT | \
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USB_LL_INTR_CORE_HCHINT)
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//Interrupt that pertain to host port events
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#define PORT_EVENTS_INTRS_MSK (USBH_LL_INTR_HPRT_PRTCONNDET | \
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USBH_LL_INTR_HPRT_PRTENCHNG | \
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USBH_LL_INTR_HPRT_PRTOVRCURRCHNG)
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/**
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* The following channel interrupt bits are currently checked (in order LSB to MSB)
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* - USBH_LL_INTR_CHAN_XFERCOMPL
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* - USBH_LL_INTR_CHAN_CHHLTD
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* - USBH_LL_INTR_CHAN_STALL
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* - USBH_LL_INTR_CHAN_BBLEER
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* - USBH_LL_INTR_CHAN_BNAINTR
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* - USBH_LL_INTR_CHAN_XCS_XACT_ERR
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*
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* Note the following points about channel interrupts:
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* - Not all bits are unmaskable under scatter/gather
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* - Those bits proxy their interrupt through the USBH_LL_INTR_CHAN_CHHLTD bit
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* - USBH_LL_INTR_CHAN_XCS_XACT_ERR is always unmasked
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* - When USBH_LL_INTR_CHAN_BNAINTR occurs, USBH_LL_INTR_CHAN_CHHLTD will NOT.
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* - USBH_LL_INTR_CHAN_AHBERR doesn't actually ever happen on our system )i.e., ESP32S2 and later):
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* - If the QTD list's starting address is an invalid address (e.g., NULL), the core will attempt to fetch that
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* address for a transfer descriptor and probably gets all zeroes. It will interpret the zero as a bad QTD and
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* return a USBH_LL_INTR_CHAN_BNAINTR instead.
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* - If the QTD's buffer pointer is an invalid address, the core will attempt to read/write data to/from that
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* invalid buffer address with NO INDICATION OF ERROR. The transfer will be acknowledged and treated as
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* successful. Bad buffer pointers MUST BE CHECKED FROM HIGHER LAYERS INSTEAD.
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*/
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#define CHAN_INTRS_EN_MSK (USBH_LL_INTR_CHAN_XFERCOMPL | \
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USBH_LL_INTR_CHAN_CHHLTD | \
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USBH_LL_INTR_CHAN_BNAINTR)
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#define CHAN_INTRS_ERROR_MSK (USBH_LL_INTR_CHAN_STALL | \
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USBH_LL_INTR_CHAN_BBLEER | \
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USBH_LL_INTR_CHAN_BNAINTR | \
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USBH_LL_INTR_CHAN_XCS_XACT_ERR)
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/* -----------------------------------------------------------------------------
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--------------------------------- Core (Global) --------------------------------
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----------------------------------------------------------------------------- */
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// ---------------------------- Private Functions ------------------------------
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static void set_defaults(usbh_hal_context_t *hal)
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{
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usbh_ll_internal_phy_conf(hal->wrap_dev); //Enable and configure internal PHY
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//GAHBCFG register
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usb_ll_en_dma_mode(hal->dev);
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usb_ll_set_hbstlen(hal->dev, 0); //INCR16 AHB burst length
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//GUSBCFG register
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usb_ll_dis_hnp_cap(hal->dev); //Disable HNP
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usb_ll_dis_srp_cap(hal->dev); //Disable SRP
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//Enable interruts
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usb_ll_dis_intrs(hal->dev, 0xFFFFFFFF); //Mask all interrupts first
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usb_ll_en_intrs(hal->dev, CORE_INTRS_EN_MSK); //Unmask global interrupts
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usb_ll_intr_read_and_clear(hal->dev); //Clear interrupts
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usb_ll_en_global_intr(hal->dev); //Enable interrupt signal
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//Enable host mode
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usb_ll_set_host_mode(hal->dev);
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}
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// ---------------------------- Public Functions -------------------------------
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void usbh_hal_init(usbh_hal_context_t *hal)
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{
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//Check if a peripheral is alive by reading the core ID registers
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usbh_dev_t *dev = &USBH;
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#ifndef NDEBUG
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uint32_t core_id = usb_ll_get_controller_core_id(dev);
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assert(core_id == CORE_REG_GSNPSID);
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#endif
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//Initialize HAL context
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memset(hal, 0, sizeof(usbh_hal_context_t));
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hal->dev = dev;
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hal->wrap_dev = &USB_WRAP;
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set_defaults(hal);
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}
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void usbh_hal_deinit(usbh_hal_context_t *hal)
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{
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//Disable and clear global interrupt
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usb_ll_dis_intrs(hal->dev, 0xFFFFFFFF); //Disable all interrupts
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usb_ll_intr_read_and_clear(hal->dev); //Clear interrupts
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usb_ll_dis_global_intr(hal->dev); //Disable interrupt signal
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hal->dev = NULL;
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hal->wrap_dev = NULL;
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}
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void usbh_hal_core_soft_reset(usbh_hal_context_t *hal)
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{
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usb_ll_core_soft_reset(hal->dev);
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while (usb_ll_check_core_soft_reset(hal->dev)) {
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; //Wait until core reset is done
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}
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while (!usb_ll_check_ahb_idle(hal->dev)) {
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; //Wait until AHB Master bus is idle before doing any other operations
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}
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//Set the default bits
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set_defaults(hal);
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//Clear all the flags and channels
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hal->flags.val = 0;
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hal->channels.num_allocd = 0;
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hal->channels.chan_pend_intrs_msk = 0;
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memset(hal->channels.hdls, 0, sizeof(usbh_hal_chan_t *) * USBH_HAL_NUM_CHAN);
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}
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/* -----------------------------------------------------------------------------
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---------------------------------- Host Port ----------------------------------
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----------------------------------------------------------------------------- */
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static inline void debounce_lock_enable(usbh_hal_context_t *hal)
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{
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//Disable the hprt (connection) and disconnection interrupts to prevent repeated triggerings
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usb_ll_dis_intrs(hal->dev, USB_LL_INTR_CORE_PRTINT | USB_LL_INTR_CORE_DISCONNINT);
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hal->flags.dbnc_lock_enabled = 1;
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}
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void usbh_hal_port_enable(usbh_hal_context_t *hal)
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{
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usb_priv_speed_t speed = usbh_ll_hprt_get_speed(hal->dev);
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//Host Configuration
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usbh_ll_hcfg_set_defaults(hal->dev, speed);
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//Todo: Set frame list entries and ena per sched
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//Configure HFIR
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usbh_ll_hfir_set_defaults(hal->dev, speed);
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//Config FIFO sizes
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usb_ll_set_rx_fifo_size(hal->dev, RX_FIFO_LEN);
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usb_ll_set_nptx_fifo_size(hal->dev, RX_FIFO_LEN, NPTX_FIFO_LEN);
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usbh_ll_set_ptx_fifo_size(hal->dev, RX_FIFO_LEN + NPTX_FIFO_LEN, PTX_FIFO_LEN);
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}
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/* -----------------------------------------------------------------------------
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----------------------------------- Channel ------------------------------------
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------------------------------------------------------------------------------*/
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// --------------------------- Channel Allocation ------------------------------
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//Allocate a channel
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bool usbh_hal_chan_alloc(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, void *chan_ctx)
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{
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//Attempt to allocate channel
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if (hal->channels.num_allocd == USBH_HAL_NUM_CHAN) {
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return false; //Out of free channels
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}
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int chan_idx = -1;
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for (int i = 0; i < USBH_HAL_NUM_CHAN; i++) {
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if (hal->channels.hdls[i] == NULL) {
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hal->channels.hdls[i] = chan_obj;
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chan_idx = i;
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hal->channels.num_allocd++;
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break;
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}
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}
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assert(chan_idx != -1);
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//Initialize channel object
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memset(chan_obj, 0, sizeof(usbh_hal_chan_t));
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chan_obj->flags.chan_idx = chan_idx;
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chan_obj->regs = usbh_ll_get_chan_regs(hal->dev, chan_idx);
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chan_obj->chan_ctx = chan_ctx;
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//Note: EP characteristics configured separately
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//Clean and unmask the channel's interrupt
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usbh_ll_chan_intr_read_and_clear(chan_obj->regs); //Clear the interrupt bits for that channel
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usbh_ll_haintmsk_en_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx);
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usbh_ll_chan_set_intr_mask(chan_obj->regs, CHAN_INTRS_EN_MSK); //Unmask interrupts for this channel
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usbh_ll_chan_set_pid(chan_obj->regs, 0); //Set the initial PID to zero
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usbh_ll_chan_hctsiz_init(chan_obj->regs); //Set the non changing parts of the HCTSIZ registers (e.g., do_ping and sched info)
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return true;
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}
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//Returns object memory
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void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj)
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{
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//Can only free a channel when in the disabled state and descriptor list released
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assert(!chan_obj->slot.flags.slot_acquired
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&& !chan_obj->flags.active
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&& !chan_obj->flags.error_pending);
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//Deallocate channel
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hal->channels.hdls[chan_obj->flags.chan_idx] = NULL;
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hal->channels.num_allocd--;
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assert(hal->channels.num_allocd >= 0);
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}
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// ---------------------------- Channel Control --------------------------------
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void usbh_hal_chan_set_ep_char(usbh_hal_chan_t *chan_obj, usbh_hal_ep_char_t *ep_char)
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{
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//Cannot change ep_char whilst channel is still active or in error
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assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
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//Set the endpoint characteristics of the pipe
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usbh_ll_chan_hcchar_init(chan_obj->regs,
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ep_char->dev_addr,
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ep_char->bEndpointAddress & BENDPOINTADDRESS_NUM_MSK,
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ep_char->mps,
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ep_char->type,
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ep_char->bEndpointAddress & BENDPOINTADDRESS_DIR_MSK,
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ep_char->ls_via_fs_hub);
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}
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/* -----------------------------------------------------------------------------
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------------------------------- Transfers Slots --------------------------------
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------------------------------------------------------------------------------*/
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void usbh_hal_chan_activate(usbh_hal_chan_t *chan_obj, int num_to_skip)
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{
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//Cannot enable a channel that has already been enabled or is pending error handling
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assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
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assert(chan_obj->slot.flags.slot_acquired);
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//Update the descriptor list index and check if it's within bounds
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chan_obj->slot.flags.cur_qtd_idx += num_to_skip;
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assert(chan_obj->slot.flags.cur_qtd_idx < chan_obj->slot.flags.qtd_list_len);
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chan_obj->flags.active = 1;
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//Set start address of the QTD list and starting QTD index
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usbh_ll_chan_set_dma_addr_non_iso(chan_obj->regs, chan_obj->slot.xfer_desc_list, chan_obj->slot.flags.cur_qtd_idx);
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//Start the channel
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usbh_ll_chan_start(chan_obj->regs);
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}
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bool usbh_hal_chan_slot_request_halt(usbh_hal_chan_t *chan_obj)
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{
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//Cannot request halt on a channel that is pending error handling
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assert(!chan_obj->flags.error_pending);
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if (usbh_ll_chan_is_active(chan_obj->regs) || chan_obj->flags.active) {
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usbh_ll_chan_halt(chan_obj->regs);
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chan_obj->flags.halt_requested = 1;
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return false;
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}
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return true;
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}
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/* -----------------------------------------------------------------------------
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-------------------------------- Event Handling --------------------------------
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----------------------------------------------------------------------------- */
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//When a device on the port is no longer valid (e.g., disconnect, port error). All channels are no longer valid
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static void chan_all_halt(usbh_hal_context_t *hal)
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{
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for (int i = 0; i < USBH_HAL_NUM_CHAN; i++) {
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if (hal->channels.hdls[i] != NULL) {
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hal->channels.hdls[i]->flags.active = 0;
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}
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}
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}
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usbh_hal_port_event_t usbh_hal_decode_intr(usbh_hal_context_t *hal)
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{
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uint32_t intrs_core = usb_ll_intr_read_and_clear(hal->dev); //Read and clear core interrupts
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uint32_t intrs_port = 0;
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if (intrs_core & USB_LL_INTR_CORE_PRTINT) {
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//There are host port interrupts. Read and clear those as well.
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intrs_port = usbh_ll_hprt_intr_read_and_clear(hal->dev);
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}
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//Note: Do not change order of checks. Regressing events (e.g. enable -> disabled, connected -> connected)
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//always take precendance. ENABLED < DISABLED < CONN < DISCONN < OVRCUR
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usbh_hal_port_event_t event = USBH_HAL_PORT_EVENT_NONE;
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//Check if this is a core or port event
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if ((intrs_core & CORE_EVENTS_INTRS_MSK) || (intrs_port & PORT_EVENTS_INTRS_MSK)) {
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//Do not change the order of the following checks. Some events/interrupts take precedence over others
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if (intrs_core & USB_LL_INTR_CORE_DISCONNINT) {
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event = USBH_HAL_PORT_EVENT_DISCONN;
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debounce_lock_enable(hal);
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chan_all_halt(hal); //All channels are halted on a disconnect
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//Mask the port connection and disconnection interrupts to prevent repeated triggering
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} else if (intrs_port & USBH_LL_INTR_HPRT_PRTOVRCURRCHNG) {
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//Check if this is an overcurrent or an overcurrent cleared
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if (usbh_ll_hprt_get_port_overcur(hal->dev)) {
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event = USBH_HAL_PORT_EVENT_OVRCUR;
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chan_all_halt(hal); //All channels are halted on an overcurrent
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} else {
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event = USBH_HAL_PORT_EVENT_OVRCUR_CLR;
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}
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} else if (intrs_port & USBH_LL_INTR_HPRT_PRTENCHNG) {
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if (usbh_ll_hprt_get_port_en(hal->dev)) { //Host port was enabled
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event = USBH_HAL_PORT_EVENT_ENABLED;
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} else { //Host port has been disabled
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event = USBH_HAL_PORT_EVENT_DISABLED;
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chan_all_halt(hal); //All channels are halted when the port is disabled
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}
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} else if (intrs_port & USBH_LL_INTR_HPRT_PRTCONNDET && !hal->flags.dbnc_lock_enabled) {
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event = USBH_HAL_PORT_EVENT_CONN;
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debounce_lock_enable(hal);
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}
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}
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//Port events always take precendance over channel events
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if (event == USBH_HAL_PORT_EVENT_NONE && (intrs_core & USB_LL_INTR_CORE_HCHINT)) {
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//One or more channels have pending interrupts. Store the mask of those channels
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hal->channels.chan_pend_intrs_msk = usbh_ll_get_chan_intrs_msk(hal->dev);
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event = USBH_HAL_PORT_EVENT_CHAN;
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}
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return event;
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}
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usbh_hal_chan_t *usbh_hal_get_chan_pending_intr(usbh_hal_context_t *hal)
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{
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int chan_num = __builtin_ffs(hal->channels.chan_pend_intrs_msk);
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if (chan_num) {
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hal->channels.chan_pend_intrs_msk &= ~(1 << (chan_num - 1)); //Clear the pending bit for that channel
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return hal->channels.hdls[chan_num - 1];
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} else {
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return NULL;
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}
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}
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usbh_hal_chan_event_t usbh_hal_chan_decode_intr(usbh_hal_chan_t *chan_obj)
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{
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uint32_t chan_intrs = usbh_ll_chan_intr_read_and_clear(chan_obj->regs);
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usbh_hal_chan_event_t chan_event;
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//Currently, all cases where channel interrupts occur will also halt the channel, except for BNA
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assert(chan_intrs & (USBH_LL_INTR_CHAN_CHHLTD | USBH_LL_INTR_CHAN_BNAINTR));
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chan_obj->flags.active = 0;
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//Note: Do not change the current checking order of checks. Certain interrupts (e.g., errors) have precedence over others
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if (chan_intrs & CHAN_INTRS_ERROR_MSK) { //One of the error interrupts has occurred.
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//Note: Errors are uncommon, so we check against the entire interrupt mask to reduce frequency of entering this call path
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//Store the error in hal context
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usbh_hal_chan_error_t error;
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if (chan_intrs & USBH_LL_INTR_CHAN_STALL) {
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error = USBH_HAL_CHAN_ERROR_STALL;
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} else if (chan_intrs & USBH_LL_INTR_CHAN_BBLEER) {
|
|
error = USBH_HAL_CHAN_ERROR_PKT_BBL;
|
|
} else if (chan_intrs & USBH_LL_INTR_CHAN_BNAINTR) {
|
|
error = USBH_HAL_CHAN_ERROR_BNA;
|
|
} else { //USBH_LL_INTR_CHAN_XCS_XACT_ERR
|
|
error = USBH_HAL_CHAN_ERROR_XCS_XACT;
|
|
}
|
|
//Update flags
|
|
chan_obj->error = error;
|
|
chan_obj->flags.error_pending = 1;
|
|
//Save the error to be handled later
|
|
chan_event = USBH_HAL_CHAN_EVENT_ERROR;
|
|
} else if (chan_obj->flags.halt_requested) { //A halt was previously requested and has not been fulfilled
|
|
chan_obj->flags.halt_requested = 0;
|
|
chan_event = USBH_HAL_CHAN_EVENT_HALT_REQ;
|
|
} else if (chan_intrs & USBH_LL_INTR_CHAN_XFERCOMPL) {
|
|
int cur_qtd_idx = usbh_ll_chan_get_ctd(chan_obj->regs);
|
|
//Store current qtd index
|
|
chan_obj->slot.flags.cur_qtd_idx = cur_qtd_idx;
|
|
if (cur_qtd_idx == 0) {
|
|
//If the transfer descriptor list has completed, the CTD index should be 0 (wrapped around)
|
|
chan_event = USBH_HAL_CHAN_EVENT_SLOT_DONE;
|
|
} else {
|
|
chan_event = USBH_HAL_CHAN_EVENT_SLOT_HALT;
|
|
}
|
|
} else {
|
|
//Should never reach this point
|
|
abort();
|
|
}
|
|
return chan_event;
|
|
}
|