Angus Gratton 654d6ee594 efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field ... 8th bit is not used by hardware. As reported https://esp32.com/viewtopic.php?f=2&t=7800&p=40895#p40894		2019-04-09 09:59:15 +10:00
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esp32	efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field	2019-04-09 09:59:15 +10:00
include/soc	heap: Add integer overflow checks on MALLOC_CAP_32BIT & MALLOC_CAP_EXEC	2019-03-21 16:05:52 +11:00
test	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
CMakeLists.txt	cmake: make main a component again	2018-09-13 11:13:27 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00