esp-idf/components/soc/esp32
2017-09-04 12:05:49 +08:00
..
include/soc Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00
test soc: implement XTAL frequency detection 2017-04-24 15:29:30 +08:00
cpu_util.c soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
i2c_apll.h soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
i2c_bbpll.h soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
i2c_rtc_clk.h soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
rtc_clk.c soc/rtc: round APB clock frequency to nearest MHz 2017-09-01 10:34:36 +08:00
rtc_init.c soc: fix typo in register name 2017-07-06 12:36:06 +08:00
rtc_pm.c soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
rtc_sleep.c sleep: add light sleep, factor out APIs common for deep/light sleep 2017-09-01 10:36:14 +08:00
rtc_time.c Add support for 32k XTAL as RTC_SLOW_CLK source 2017-04-26 12:43:22 +08:00
soc_log.h soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
soc_memory_layout.c heap: Rename memory "tags" to "types" to avoid confusion w/ old tag allocator API 2017-07-10 17:46:03 +08:00