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145 lines
6.3 KiB
Plaintext
145 lines
6.3 KiB
Plaintext
menu "ESP System Settings"
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choice ESP_SYSTEM_PANIC
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prompt "Panic handler behaviour"
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default ESP_SYSTEM_PANIC_PRINT_REBOOT
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help
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If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
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invoked. Configure the panic handler's action here.
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config ESP_SYSTEM_PANIC_PRINT_HALT
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bool "Print registers and halt"
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help
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Outputs the relevant registers over the serial port and halt the
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processor. Needs a manual reset to restart.
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config ESP_SYSTEM_PANIC_PRINT_REBOOT
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bool "Print registers and reboot"
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help
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Outputs the relevant registers over the serial port and immediately
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reset the processor.
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config ESP_SYSTEM_PANIC_SILENT_REBOOT
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bool "Silent reboot"
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help
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Just resets the processor without outputting anything
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config ESP_SYSTEM_PANIC_GDBSTUB
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bool "Invoke GDBStub"
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select ESP_GDBSTUB_ENABLED
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
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of the crash.
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endchoice
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config ESP_SYSTEM_SINGLE_CORE_MODE
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bool
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default n
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help
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Only initialize and use the main core.
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config ESP_SYSTEM_RTC_EXT_XTAL
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on
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bool
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default n
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config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
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int "Bootstrap cycles for external 32kHz crystal"
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depends on ESP_SYSTEM_RTC_EXT_XTAL
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default 5 if IDF_TARGET_ESP32
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default 0
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range 0 32768
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help
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To reduce the startup time of an external RTC crystal,
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we bootstrap it with a 32kHz square wave for a fixed number of cycles.
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Setting 0 will disable bootstrapping (if disabled, the crystal may take
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longer to start up or fail to oscillate under some conditions).
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If this value is too high, a faulty crystal may initially start and then fail.
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If this value is too low, an otherwise good crystal may not start.
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To accurately determine if the crystal has started,
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set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
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config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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bool
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default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE
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default y if IDF_TARGET_ESP32S2
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default y if IDF_TARGET_ESP32C3
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default y if IDF_TARGET_ESP32S3
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config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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bool "Enable RTC fast memory for dynamic allocations"
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default y if IDF_TARGET_ESP32
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default y if IDF_TARGET_ESP32S2
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default y if IDF_TARGET_ESP32C3
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default n if IDF_TARGET_ESP32S3 # TODO
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depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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help
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This config option allows to add RTC fast memory region to system heap with capability
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similar to that of DRAM region but without DMA. This memory will be consumed first per
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heap initialization order by early startup services and scheduler related code. Speed
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wise RTC fast memory operates on APB clock and hence does not have much performance impact.
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config ESP_SYSTEM_PD_FLASH
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bool "PD flash at light sleep when there is no SPIRAM"
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depends on !SPIRAM
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default y
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help
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If enabled, chip will try to power down flash at light sleep, which costs more time when chip wakes up.
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Can only be enabled if there is no SPIRAM configured. This option will in fact consider VDD_SDIO auto power
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value (ESP_PD_OPTION_AUTO) as OFF. Also, it is possible to force a power domain to stay ON during light
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sleep by using esp_sleep_pd_config() function.
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config ESP_SYSTEM_PM_POWER_DOWN_CPU
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bool "Power down CPU in light sleep"
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depends on IDF_TARGET_ESP32C3
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default y
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help
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If enabled, the CPU will be powered down in light sleep. Enabling this option will consume
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1.68 KB of internal RAM and will reduce sleep current consumption by about 100 uA.
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config ESP_SYSTEM_PSRAM_LEAKAGE_WORKAROUND
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bool "PSRAM leakage current workaround in light sleep"
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depends on SPIRAM
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help
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When the CS pin of SPIRAM is not pulled up, the sleep current will
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increase during light sleep. If the CS pin of SPIRAM has an external
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pull-up, you do not need to select this option, otherwise, you
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should enable this option.
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config ESP_SYSTEM_FLASH_LEAKAGE_WORKAROUND
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bool "Flash leakage current workaround in light sleep"
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help
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When the CS pin of Flash is not pulled up, the sleep current will
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increase during light sleep. If the CS pin of Flash has an external
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pull-up, you do not need to select this option, otherwise, you
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should enable this option.
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menu "Memory protection"
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config ESP_SYSTEM_MEMPROT_FEATURE
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bool "Enable memory protection"
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depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S2
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default "y"
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help
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If enabled, the permission control module watches all the memory access and fires the panic handler
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if a permission violation is detected. This feature automatically splits
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the SRAM memory into data and instruction segments and sets Read/Execute permissions
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for the instruction part (below given splitting address) and Read/Write permissions
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for the data part (above the splitting address). The memory protection is effective
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on all access through the IRAM0 and DRAM0 buses.
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config ESP_SYSTEM_MEMPROT_FEATURE_LOCK
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depends on ESP_SYSTEM_MEMPROT_FEATURE
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bool "Lock memory protection settings"
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default "y"
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help
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Once locked, memory protection settings cannot be changed anymore.
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The lock is reset only on the chip startup.
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endmenu # Memory protection
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endmenu # ESP System Settings
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