mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
29accf2533
Note: on ESP32 UART rxfifo seems to be read as u8 instead of u32 to make it work
252 lines
9.0 KiB
C
252 lines
9.0 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SYS_TIMER_STRUCT_H_
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#define _SOC_SYS_TIMER_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct sys_timer_dev_s {
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union {
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struct {
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uint32_t systimer_clk_fo: 1; /*systimer clock force on*/
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uint32_t reserved1: 21;
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uint32_t target2_work_en: 1; /*target2 work enable*/
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uint32_t target1_work_en: 1; /*target1 work enable*/
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uint32_t target0_work_en: 1; /*target0 work enable*/
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uint32_t timer_unit1_core1_stall_en: 1; /*If timer unit1 is stalled when core1 stalled*/
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uint32_t timer_unit1_core0_stall_en: 1; /*If timer unit1 is stalled when core0 stalled*/
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uint32_t timer_unit0_core1_stall_en: 1; /*If timer unit0 is stalled when core1 stalled*/
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uint32_t timer_unit0_core0_stall_en: 1; /*If timer unit0 is stalled when core0 stalled*/
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uint32_t timer_unit1_work_en: 1; /*timer unit1 work enable*/
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uint32_t timer_unit0_work_en: 1; /*timer unit0 work enable*/
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uint32_t clk_en: 1; /*register file clk gating*/
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};
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uint32_t val;
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} systimer_conf;
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union {
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struct {
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uint32_t reserved0: 29;
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uint32_t timer_unit0_value_valid: 1;
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uint32_t timer_unit0_update: 1; /*update timer_unit0*/
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} systimer_unit0_op;
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union {
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struct {
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uint32_t reserved0: 29;
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uint32_t timer_unit1_value_valid: 1; /*timer value is sync and valid*/
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uint32_t timer_unit1_update: 1; /*update timer unit1*/
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} systimer_unit1_op;
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union {
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struct {
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uint32_t timer_unit0_load_hi:20; /*timer unit0 load high 32 bit*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_unit0_load_hi;
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uint32_t systimer_unit0_load_lo; /**/
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union {
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struct {
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uint32_t timer_unit1_load_hi:20; /*timer unit1 load high 32 bit*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_unit1_load_hi;
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uint32_t systimer_unit1_load_lo; /**/
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union {
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struct {
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uint32_t timer_target0_hi:20; /*timer taget0 high 32 bit*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_target0_hi;
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uint32_t systimer_target0_lo; /**/
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union {
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struct {
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uint32_t timer_target1_hi:20; /*timer taget1 high 32 bit*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_target1_hi;
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uint32_t systimer_target1_lo; /**/
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union {
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struct {
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uint32_t timer_target2_hi:20; /*timer taget2 high 32 bit*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_target2_hi;
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uint32_t systimer_target2_lo; /**/
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union {
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struct {
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uint32_t target0_period: 26; /*target0 period*/
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uint32_t reserved26: 4;
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uint32_t target0_period_mode: 1; /*Set target0 to period mode*/
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uint32_t target0_timer_unit_sel: 1; /*select which unit to compare*/
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};
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uint32_t val;
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} systimer_target0_conf;
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union {
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struct {
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uint32_t target1_period: 26; /*target1 period*/
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uint32_t reserved26: 4;
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uint32_t target1_period_mode: 1; /*Set target1 to period mode*/
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uint32_t target1_timer_unit_sel: 1; /*select which unit to compare*/
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};
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uint32_t val;
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} systimer_target1_conf;
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union {
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struct {
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uint32_t target2_period: 26; /*target2 period*/
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uint32_t reserved26: 4;
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uint32_t target2_period_mode: 1; /*Set target2 to period mode*/
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uint32_t target2_timer_unit_sel: 1; /*select which unit to compare*/
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};
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uint32_t val;
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} systimer_target2_conf;
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union {
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struct {
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uint32_t timer_unit0_value_hi:20; /*timer read value high 32bit*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_unit0_value_hi;
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uint32_t systimer_unit0_value_lo; /**/
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union {
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struct {
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uint32_t timer_unit1_value_hi:20; /*timer read value high 32bit*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} systimer_unit1_value_hi;
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uint32_t systimer_unit1_value_lo; /**/
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union {
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struct {
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uint32_t timer_comp0_load: 1; /*timer comp0 load value*/
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uint32_t reserved1: 31;
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};
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uint32_t val;
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} systimer_comp0_load;
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union {
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struct {
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uint32_t timer_comp1_load: 1; /*timer comp1 load value*/
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uint32_t reserved1: 31;
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};
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uint32_t val;
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} systimer_comp1_load;
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union {
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struct {
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uint32_t timer_comp2_load: 1; /*timer comp2 load value*/
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uint32_t reserved1: 31;
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};
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uint32_t val;
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} systimer_comp2_load;
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union {
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struct {
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uint32_t timer_unit0_load: 1; /*timer unit0 load value*/
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uint32_t reserved1: 31;
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};
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uint32_t val;
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} systimer_unit0_load;
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union {
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struct {
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uint32_t timer_unit1_load: 1; /*timer unit1 load value*/
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uint32_t reserved1: 31;
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};
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uint32_t val;
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} systimer_unit1_load;
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union {
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struct {
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uint32_t target0: 1; /*interupt0 enable*/
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uint32_t target1: 1; /*interupt1 enable*/
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uint32_t target2: 1; /*interupt2 enable*/
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} systimer_int_ena;
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union {
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struct {
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uint32_t target0: 1; /*interupt0 raw*/
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uint32_t target1: 1; /*interupt1 raw*/
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uint32_t target2: 1; /*interupt2 raw*/
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} systimer_int_raw;
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union {
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struct {
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uint32_t target0: 1; /*interupt0 clear*/
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uint32_t target1: 1; /*interupt1 clear*/
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uint32_t target2: 1; /*interupt2 clear*/
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} systimer_int_clr;
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union {
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struct {
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uint32_t target0: 1;
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uint32_t target1: 1;
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uint32_t target2: 1;
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} systimer_int_st;
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uint32_t reserved_74;
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uint32_t reserved_78;
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uint32_t reserved_7c;
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uint32_t reserved_80;
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uint32_t reserved_84;
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uint32_t reserved_88;
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uint32_t reserved_8c;
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uint32_t reserved_90;
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uint32_t reserved_94;
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uint32_t reserved_98;
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uint32_t reserved_9c;
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uint32_t reserved_a0;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t reserved_f8;
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uint32_t systimer_date; /**/
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} sys_timer_dev_t;
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extern sys_timer_dev_t SYS_TIMER;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_SYS_TIMER_STRUCT_H_ */
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