mirror of
https://github.com/espressif/esp-idf.git
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248 lines
10 KiB
C
248 lines
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/queue.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "driver/gpio.h"
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#include "esp_clock_output.h"
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#include "esp_check.h"
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#include "esp_rom_gpio.h"
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#include "soc/clkout_channel.h"
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#include "hal/gpio_hal.h"
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "soc/soc_caps.h"
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#include "soc/io_mux_reg.h"
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typedef struct clkout_channel_handle {
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bool is_mapped;
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soc_clkout_sig_id_t mapped_clock;
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clock_out_channel_t channel_id;
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uint8_t ref_cnt;
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uint64_t mapped_io_bmap;
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portMUX_TYPE clkout_channel_lock;
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} clkout_channel_handle_t;
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typedef struct esp_clock_output_mapping {
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gpio_num_t mapped_io;
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clkout_channel_handle_t* clkout_channel_hdl;
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uint8_t ref_cnt;
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portMUX_TYPE clkout_mapping_lock;
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SLIST_ENTRY(esp_clock_output_mapping) next;
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} esp_clock_output_mapping_t;
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static const char *TAG = "esp_clock_output";
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static SLIST_HEAD(esp_clock_output_mapping_head, esp_clock_output_mapping) s_mapping_list = SLIST_HEAD_INITIALIZER(s_mapping_list_head);
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static portMUX_TYPE s_mapping_list_lock = portMUX_INITIALIZER_UNLOCKED;
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static portMUX_TYPE s_clkout_lock = portMUX_INITIALIZER_UNLOCKED;
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static clkout_channel_handle_t s_clkout_handle[CLKOUT_CHANNEL_MAX] = {
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[0 ... CLKOUT_CHANNEL_MAX - 1] = {
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.is_mapped = false,
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.ref_cnt = 0,
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.mapped_io_bmap = 0,
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.clkout_channel_lock = portMUX_INITIALIZER_UNLOCKED,
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}
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};
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static clkout_channel_handle_t* clkout_channel_alloc(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num)
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{
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clkout_channel_handle_t *allocated_channel = NULL;
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#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
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portENTER_CRITICAL(&s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].clkout_channel_lock);
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if (!s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].is_mapped) {
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s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].is_mapped = true;
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allocated_channel = &s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)];
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} else if ((s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].mapped_io_bmap & BIT(gpio_num)) &&
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(s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].mapped_clock == clk_sig)) {
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allocated_channel = &s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)];
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}
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if (allocated_channel != NULL) {
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allocated_channel->channel_id = (clock_out_channel_t)IONUM_TO_CLKOUT_CHANNEL(gpio_num);
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}
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portEXIT_CRITICAL(&s_clkout_handle[IONUM_TO_CLKOUT_CHANNEL(gpio_num)].clkout_channel_lock);
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#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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for (uint32_t channel = 0; channel < CLKOUT_CHANNEL_MAX; channel++) {
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portENTER_CRITICAL(&s_clkout_handle[channel].clkout_channel_lock);
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if (!s_clkout_handle[channel].is_mapped) {
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s_clkout_handle[channel].is_mapped = true;
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allocated_channel = &s_clkout_handle[channel];
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allocated_channel->channel_id = (clock_out_channel_t)channel;
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portEXIT_CRITICAL(&s_clkout_handle[channel].clkout_channel_lock);
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break;
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} else if (s_clkout_handle[channel].mapped_clock == clk_sig) {
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allocated_channel = &s_clkout_handle[channel];
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portEXIT_CRITICAL(&s_clkout_handle[channel].clkout_channel_lock);
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break;
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}
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portEXIT_CRITICAL(&s_clkout_handle[channel].clkout_channel_lock);
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}
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#endif
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if (allocated_channel != NULL) {
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portENTER_CRITICAL(&allocated_channel->clkout_channel_lock);
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allocated_channel->mapped_io_bmap |= BIT(gpio_num);
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allocated_channel->mapped_clock = clk_sig;
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allocated_channel->ref_cnt++;
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if (allocated_channel->ref_cnt == 1) {
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portENTER_CRITICAL(&s_clkout_lock);
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#if SOC_CLOCKOUT_HAS_SOURCE_GATE
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clk_ll_enable_clkout_source(clk_sig, true);
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#endif
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clk_hal_clock_output_setup(clk_sig, allocated_channel->channel_id);
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portEXIT_CRITICAL(&s_clkout_lock);
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}
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portEXIT_CRITICAL(&allocated_channel->clkout_channel_lock);
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}
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return allocated_channel;
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}
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static esp_clock_output_mapping_t* clkout_mapping_alloc(clkout_channel_handle_t* channel_hdl, gpio_num_t gpio_num)
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{
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esp_clock_output_mapping_t *allocated_mapping = NULL;
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portENTER_CRITICAL(&s_mapping_list_lock);
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esp_clock_output_mapping_t *hdl;
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SLIST_FOREACH(hdl, &s_mapping_list, next) {
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if ((hdl->clkout_channel_hdl == channel_hdl) && (hdl->mapped_io == gpio_num)) {
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allocated_mapping = hdl;
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}
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}
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portEXIT_CRITICAL(&s_mapping_list_lock);
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if (allocated_mapping == NULL) {
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allocated_mapping = (esp_clock_output_mapping_t *)malloc(sizeof(esp_clock_output_mapping_t));
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if (!allocated_mapping) {
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return NULL;
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}
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allocated_mapping->mapped_io = gpio_num;
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allocated_mapping->clkout_channel_hdl = channel_hdl;
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allocated_mapping->ref_cnt = 0;
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portMUX_INITIALIZE(&allocated_mapping->clkout_mapping_lock);
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portENTER_CRITICAL(&s_mapping_list_lock);
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SLIST_INSERT_HEAD(&s_mapping_list, allocated_mapping, next);
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portEXIT_CRITICAL(&s_mapping_list_lock);
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}
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portENTER_CRITICAL(&allocated_mapping->clkout_mapping_lock);
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allocated_mapping->ref_cnt++;
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if (allocated_mapping->ref_cnt == 1) {
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#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], CLKOUT_CHANNEL_TO_IOMUX_FUNC(allocated_mapping->clkout_channel_hdl->channel_id));
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#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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gpio_set_pull_mode(gpio_num, GPIO_FLOATING);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
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esp_rom_gpio_connect_out_signal(gpio_num, CLKOUT_CHANNEL_TO_GPIO_SIG_ID(allocated_mapping->clkout_channel_hdl->channel_id), false, false);
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#endif
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}
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portEXIT_CRITICAL(&allocated_mapping->clkout_mapping_lock);
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return allocated_mapping;
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}
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static void clkout_channel_free(clkout_channel_handle_t *channel_hdl)
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{
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portENTER_CRITICAL(&channel_hdl->clkout_channel_lock);
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if (--channel_hdl->ref_cnt == 0) {
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portENTER_CRITICAL(&s_clkout_lock);
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#if SOC_CLOCKOUT_HAS_SOURCE_GATE
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clk_ll_enable_clkout_source(channel_hdl->mapped_clock, false);
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#endif
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clk_hal_clock_output_teardown(channel_hdl->channel_id);
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portEXIT_CRITICAL(&s_clkout_lock);
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channel_hdl->mapped_clock = CLKOUT_SIG_INVALID;
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channel_hdl->is_mapped = false;
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}
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portEXIT_CRITICAL(&channel_hdl->clkout_channel_lock);
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}
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static void clkout_mapping_free(esp_clock_output_mapping_t *mapping_hdl)
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{
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portENTER_CRITICAL(&mapping_hdl->clkout_mapping_lock);
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clkout_channel_free(mapping_hdl->clkout_channel_hdl);
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bool do_free_mapping_hdl = false;
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if (--mapping_hdl->ref_cnt == 0) {
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[mapping_hdl->mapped_io], PIN_FUNC_GPIO);
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esp_rom_gpio_connect_out_signal(mapping_hdl->mapped_io, SIG_GPIO_OUT_IDX, false, false);
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gpio_set_direction(mapping_hdl->mapped_io, GPIO_MODE_DISABLE);
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portENTER_CRITICAL(&mapping_hdl->clkout_channel_hdl->clkout_channel_lock);
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mapping_hdl->clkout_channel_hdl->mapped_io_bmap &= ~BIT(mapping_hdl->mapped_io);
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portEXIT_CRITICAL(&mapping_hdl->clkout_channel_hdl->clkout_channel_lock);
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portENTER_CRITICAL(&s_mapping_list_lock);
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SLIST_REMOVE(&s_mapping_list, mapping_hdl, esp_clock_output_mapping, next);
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portEXIT_CRITICAL(&s_mapping_list_lock);
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do_free_mapping_hdl = true;
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}
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portEXIT_CRITICAL(&mapping_hdl->clkout_mapping_lock);
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if (do_free_mapping_hdl) {
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free(mapping_hdl);
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}
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}
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esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, esp_clock_output_mapping_handle_t *clkout_mapping_ret_hdl)
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{
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ESP_RETURN_ON_FALSE((clkout_mapping_ret_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out mapping handle passed in is invalid");
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#if SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "%s", "Output GPIO number error");
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#else
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ESP_RETURN_ON_FALSE(IS_VALID_CLKOUT_IO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "%s", "Output GPIO number error");
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#endif
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esp_clock_output_mapping_t *hdl;
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SLIST_FOREACH(hdl, &s_mapping_list, next) {
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ESP_RETURN_ON_FALSE(!((hdl->mapped_io == gpio_num) && (hdl->clkout_channel_hdl->mapped_clock != clk_sig)), ESP_ERR_INVALID_ARG, TAG, "Selected io is already mapped by another signal");
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}
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clkout_channel_handle_t *channel_hdl = clkout_channel_alloc(clk_sig, gpio_num);
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#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
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ESP_RETURN_ON_FALSE((channel_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Selected clock out IO is already mapped to other internal clock source");
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#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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ESP_RETURN_ON_FALSE((channel_hdl != NULL), ESP_FAIL, TAG, "Maximum support for %d output clock signals, no available clock_out channel for assignment", CLKOUT_CHANNEL_MAX);
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#endif
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*clkout_mapping_ret_hdl = clkout_mapping_alloc(channel_hdl, gpio_num);
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return ESP_OK;
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}
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esp_err_t esp_clock_output_stop(esp_clock_output_mapping_handle_t clkout_mapping_hdl)
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{
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ESP_RETURN_ON_FALSE((clkout_mapping_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out mapping handle passed in is invalid");
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ESP_RETURN_ON_FALSE(clkout_mapping_hdl->ref_cnt > 0, ESP_ERR_INVALID_STATE, TAG, "%s", "Clock outputting is already disabled");
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clkout_mapping_free(clkout_mapping_hdl);
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return ESP_OK;
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}
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#if SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER
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esp_err_t esp_clock_output_set_divider(esp_clock_output_mapping_handle_t clkout_mapping_hdl, uint32_t div_num)
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{
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ESP_RETURN_ON_FALSE(((div_num > 0) && (div_num <= 256)), ESP_ERR_INVALID_ARG, TAG, "Divider number must be in the range of [1, 256]");
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ESP_RETURN_ON_FALSE((clkout_mapping_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out mapping handle passed in is invalid");
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portENTER_CRITICAL(&clkout_mapping_hdl->clkout_mapping_lock);
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clk_hal_clock_output_set_divider(clkout_mapping_hdl->clkout_channel_hdl->channel_id, div_num);
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portEXIT_CRITICAL(&clkout_mapping_hdl->clkout_mapping_lock);
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return ESP_OK;
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}
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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// Due to a hardware bug, PIN_CTRL cannot select 0xf output, whereas 0xf is the default value.
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__attribute__((constructor))
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static void esp_clock_output_pin_ctrl_init(void)
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{
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gpio_ll_set_pin_ctrl(0, CLK_OUT1, CLK_OUT1_S);
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gpio_ll_set_pin_ctrl(0, CLK_OUT2, CLK_OUT2_S);
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gpio_ll_set_pin_ctrl(0, CLK_OUT3, CLK_OUT3_S);
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}
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#endif
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