esp-idf/components/riscv/include/riscv
Sudeep Mohanty 459ff8348f fix(riscv): Added RISC-V functions to set interrupt threshold for CLIC targets
This commit added the RISC-V utility functions to set the interrupt
threshold for CLIC targets by using direct register value writes.
This makes the functions more efficient during run-time.
This is done to improve the critical section enter and exit performance on esp32p4.
2024-02-28 08:51:37 +01:00
..
csr.h fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting 2023-11-16 18:11:57 +08:00
encoding.h riscv: Add new arch-level component 2020-11-12 09:33:18 +11:00
instruction_decode.h refactor(tools): Tidy up core component files copyright ignore 2024-01-22 18:07:35 +08:00
interrupt.h refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
rv_utils.h fix(riscv): Added RISC-V functions to set interrupt threshold for CLIC targets 2024-02-28 08:51:37 +01:00
rvruntime-frames.h fix(riscv): adjust TCBs lowest stack address when the FPU is used 2024-01-18 13:06:29 +08:00
rvsleep-frames.h bugfix: fix pmp retention and add pma retention 2023-05-29 16:35:03 +08:00
semihosting.h semihosting: version 2 2022-05-05 09:12:42 +00:00