Jiang Jiang Jian e0286e24c8 Merge branch 'bugfix/lp_active_slow_clock_domain_default_power_down_v5.2' into 'release/v5.2'
backport v5.2: In the LP ACTIVE state, the slow clock power domain is by default in a powered-off state

See merge request espressif/esp-idf!26998
2023-11-09 12:14:24 +08:00
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