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https://github.com/espressif/esp-idf.git
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127 lines
4.0 KiB
C
127 lines
4.0 KiB
C
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_system.h"
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#include "esp32/rom/rtc.h"
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#include "esp_private/system_internal.h"
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#include "soc/rtc_periph.h"
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static void esp_reset_reason_clear_hint(void);
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static esp_reset_reason_t s_reset_reason;
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static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
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{
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switch (rtc_reset_reason) {
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case POWERON_RESET:
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return ESP_RST_POWERON;
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/* For ESP32, ESP_RST_EXT is never returned */
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case SW_CPU_RESET:
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case SW_RESET:
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case EXT_CPU_RESET: /* unused */
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if (reset_reason_hint == ESP_RST_PANIC ||
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reset_reason_hint == ESP_RST_BROWNOUT ||
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reset_reason_hint == ESP_RST_TASK_WDT ||
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reset_reason_hint == ESP_RST_INT_WDT) {
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return reset_reason_hint;
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}
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return ESP_RST_SW;
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case DEEPSLEEP_RESET:
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return ESP_RST_DEEPSLEEP;
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case TG0WDT_SYS_RESET:
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return ESP_RST_TASK_WDT;
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case TG1WDT_SYS_RESET:
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return ESP_RST_INT_WDT;
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case OWDT_RESET:
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case RTCWDT_SYS_RESET:
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case RTCWDT_RTC_RESET:
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case RTCWDT_CPU_RESET: /* unused */
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case TGWDT_CPU_RESET: /* unused */
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return ESP_RST_WDT;
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case RTCWDT_BROWN_OUT_RESET: /* unused */
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return ESP_RST_BROWNOUT;
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case SDIO_RESET:
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return ESP_RST_SDIO;
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case INTRUSION_RESET: /* unused */
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default:
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return ESP_RST_UNKNOWN;
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}
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}
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static void __attribute__((constructor)) esp_reset_reason_init(void)
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{
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esp_reset_reason_t hint = esp_reset_reason_get_hint();
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s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM),
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hint);
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if (hint != ESP_RST_UNKNOWN) {
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esp_reset_reason_clear_hint();
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}
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}
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esp_reset_reason_t esp_reset_reason(void)
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{
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return s_reset_reason;
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}
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/* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG,
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* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
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* deep sleep wake stub entry address and for reset reason hint, since wake stub
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* is only used for deep sleep reset, and in this case the reason provided by
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* rtc_get_reset_reason is unambiguous.
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*
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* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
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* the value is replicated in low and high half-words. In addition to that,
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* MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
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* deep sleep wake stub address.
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*/
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#define RST_REASON_BIT 0x80000000
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#define RST_REASON_MASK 0x7FFF
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#define RST_REASON_SHIFT 16
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/* in IRAM, can be called from panic handler */
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void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
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{
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assert((hint & (~RST_REASON_MASK)) == 0);
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uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
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REG_WRITE(RTC_RESET_CAUSE_REG, val);
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}
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/* in IRAM, can be called from panic handler */
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esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void)
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{
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uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
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uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;
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uint32_t low = reset_reason_hint & RST_REASON_MASK;
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if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) {
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return ESP_RST_UNKNOWN;
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}
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return (esp_reset_reason_t) low;
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}
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static void esp_reset_reason_clear_hint(void)
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{
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REG_WRITE(RTC_RESET_CAUSE_REG, 0);
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}
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