mirror of
https://github.com/espressif/esp-idf.git
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357 lines
11 KiB
C
357 lines
11 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Data Memory */
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/** Group: Configuration registers */
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/** Type of conf register
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* ECDSA configure register
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*/
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typedef union {
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struct {
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/** work_mode : R/W; bitpos: [1:0]; default: 0;
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* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
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* Generate Mode. 2: Export Public Key Mode. 3: invalid.
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*/
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uint32_t work_mode:2;
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/** ecc_curve : R/W; bitpos: [2]; default: 0;
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* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
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*/
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uint32_t ecc_curve:1;
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/** software_set_k : R/W; bitpos: [3]; default: 0;
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* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
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* written by software.
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*/
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uint32_t software_set_k:1;
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/** software_set_z : R/W; bitpos: [4]; default: 0;
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* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
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* software.
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*/
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uint32_t software_set_z:1;
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/** deterministic_k : R/W; bitpos: [5]; default: 0;
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* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
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* deterministic derivation algorithm.
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*/
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uint32_t deterministic_k:1;
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/** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
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* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
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*/
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uint32_t deterministic_loop:16;
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uint32_t reserved_22:10;
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};
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uint32_t val;
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} ecdsa_conf_reg_t;
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/** Type of start register
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* ECDSA start register
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*/
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typedef union {
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struct {
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/** start : WT; bitpos: [0]; default: 0;
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* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
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* after configuration.
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*/
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uint32_t start:1;
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/** load_done : WT; bitpos: [1]; default: 0;
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* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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uint32_t load_done:1;
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/** get_done : WT; bitpos: [2]; default: 0;
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* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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uint32_t get_done:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} ecdsa_start_reg_t;
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/** Group: Clock and reset registers */
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/** Type of clk register
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* ECDSA clock gate register
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*/
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typedef union {
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struct {
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/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
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* Write 1 to force on register clock gate.
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*/
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uint32_t clk_gate_force_on:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} ecdsa_clk_reg_t;
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/** Group: Interrupt registers */
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/** Type of int_raw register
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* ECDSA interrupt raw register, valid in level.
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*/
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typedef union {
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struct {
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/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
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*/
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uint32_t prep_done_int_raw:1;
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/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
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*/
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uint32_t proc_done_int_raw:1;
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/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the ecdsa_post_done_int interrupt
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*/
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uint32_t post_done_int_raw:1;
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/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
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* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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uint32_t sha_release_int_raw:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ecdsa_int_raw_reg_t;
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/** Type of int_st register
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* ECDSA interrupt status register.
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*/
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typedef union {
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struct {
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/** prep_done_int_st : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
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*/
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uint32_t prep_done_int_st:1;
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/** proc_done_int_st : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
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*/
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uint32_t proc_done_int_st:1;
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/** post_done_int_st : RO; bitpos: [2]; default: 0;
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* The masked interrupt status bit for the ecdsa_post_done_int interrupt
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*/
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uint32_t post_done_int_st:1;
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/** sha_release_int_st : RO; bitpos: [3]; default: 0;
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* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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uint32_t sha_release_int_st:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ecdsa_int_st_reg_t;
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/** Type of int_ena register
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* ECDSA interrupt enable register.
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*/
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typedef union {
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struct {
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/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the ecdsa_prep_done_int interrupt
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*/
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uint32_t prep_done_int_ena:1;
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/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the ecdsa_proc_done_int interrupt
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*/
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uint32_t proc_done_int_ena:1;
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/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
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* The interrupt enable bit for the ecdsa_post_done_int interrupt
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*/
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uint32_t post_done_int_ena:1;
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/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
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* The interrupt enable bit for the ecdsa_sha_release_int interrupt
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*/
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uint32_t sha_release_int_ena:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ecdsa_int_ena_reg_t;
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/** Type of int_clr register
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* ECDSA interrupt clear register.
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*/
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typedef union {
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struct {
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/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the ecdsa_prep_done_int interrupt
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*/
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uint32_t prep_done_int_clr:1;
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/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the ecdsa_proc_done_int interrupt
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*/
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uint32_t proc_done_int_clr:1;
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/** post_done_int_clr : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the ecdsa_post_done_int interrupt
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*/
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uint32_t post_done_int_clr:1;
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/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
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* Set this bit to clear the ecdsa_sha_release_int interrupt
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*/
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uint32_t sha_release_int_clr:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} ecdsa_int_clr_reg_t;
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/** Group: Status registers */
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/** Type of state register
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* ECDSA status register
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*/
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typedef union {
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struct {
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/** busy : RO; bitpos: [1:0]; default: 0;
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* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
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* state.
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*/
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uint32_t busy:2;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} ecdsa_state_reg_t;
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/** Group: Result registers */
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/** Type of result register
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* ECDSA result register
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*/
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typedef union {
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struct {
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/** operation_result : RO/SS; bitpos: [0]; default: 0;
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* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
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* done.
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*/
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uint32_t operation_result:1;
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/** k_value_warning : RO/SS; bitpos: [1]; default: 0;
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* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
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* curve order, then actually taken k = k mod n.
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*/
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uint32_t k_value_warning:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} ecdsa_result_reg_t;
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/** Group: SHA register */
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/** Type of sha_mode register
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* ECDSA control SHA register
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*/
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typedef union {
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struct {
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/** sha_mode : R/W; bitpos: [2:0]; default: 0;
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* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
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* Others: invalid.
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*/
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uint32_t sha_mode:3;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} ecdsa_sha_mode_reg_t;
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/** Type of sha_start register
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* ECDSA control SHA register
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*/
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typedef union {
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struct {
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/** sha_start : WT; bitpos: [0]; default: 0;
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* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
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* bit will be self-cleared after configuration.
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*/
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uint32_t sha_start:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} ecdsa_sha_start_reg_t;
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/** Type of sha_continue register
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* ECDSA control SHA register
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*/
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typedef union {
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struct {
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/** sha_continue : WT; bitpos: [0]; default: 0;
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* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
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* bit will be self-cleared after configuration.
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*/
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uint32_t sha_continue:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} ecdsa_sha_continue_reg_t;
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/** Type of sha_busy register
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* ECDSA status register
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*/
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typedef union {
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struct {
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/** sha_busy : RO; bitpos: [0]; default: 0;
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* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
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* calculation. 0: SHA is idle.
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*/
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uint32_t sha_busy:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} ecdsa_sha_busy_reg_t;
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/** Group: Version register */
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/** Type of date register
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* Version control register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 36725040;
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* ECDSA version control register
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} ecdsa_date_reg_t;
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typedef struct {
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uint32_t reserved_000;
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volatile ecdsa_conf_reg_t conf;
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volatile ecdsa_clk_reg_t clk;
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volatile ecdsa_int_raw_reg_t int_raw;
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volatile ecdsa_int_st_reg_t int_st;
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volatile ecdsa_int_ena_reg_t int_ena;
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volatile ecdsa_int_clr_reg_t int_clr;
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volatile ecdsa_start_reg_t start;
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volatile ecdsa_state_reg_t state;
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volatile ecdsa_result_reg_t result;
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uint32_t reserved_028[53];
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volatile ecdsa_date_reg_t date;
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uint32_t reserved_100[64];
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volatile ecdsa_sha_mode_reg_t sha_mode;
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uint32_t reserved_204[3];
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volatile ecdsa_sha_start_reg_t sha_start;
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volatile ecdsa_sha_continue_reg_t sha_continue;
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volatile ecdsa_sha_busy_reg_t sha_busy;
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uint32_t reserved_21c[25];
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volatile uint32_t message[8];
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uint32_t reserved_2a0[40];
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volatile uint32_t r[8];
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volatile uint32_t s[8];
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volatile uint32_t z[8];
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volatile uint32_t qax[8];
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volatile uint32_t qay[8];
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} ecdsa_dev_t;
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extern ecdsa_dev_t ECDSA;
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#ifndef __cplusplus
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_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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