mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
926 lines
33 KiB
C
926 lines
33 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Registers */
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/** Type of strap register
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* Strapping pin register
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*/
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typedef union {
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struct {
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/** strapping : RO; bitpos: [15:0]; default: 0;
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* Represents the values of GPIO strapping pins.
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*
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* - bit0 ~ bit1: invalid
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* - bit2: GPIO8
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* - bit3: GPIO9
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* - bit4: GPIO7
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* - bit5 ~ bit15: invalid
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*/
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uint32_t strapping:16;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} gpio_strap_reg_t;
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/** Type of out register
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* GPIO output register
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*/
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typedef union {
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struct {
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/** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0;
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* Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\
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* 0: Low level\\
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* 1: High level\\
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* The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24
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* respectively. Bit25 ~ bit31 are invalid.\\
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*/
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uint32_t out_data_orig:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_out_reg_t;
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/** Type of out_w1ts register
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* GPIO output set register
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*/
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typedef union {
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struct {
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/** out_w1ts : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
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* GPIO24.\\
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* 0: Not set\\
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* 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to set GPIO_OUT_REG. \\
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*/
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uint32_t out_w1ts:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_out_w1ts_reg_t;
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/** Type of out_w1tc register
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* GPIO output clear register
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*/
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typedef union {
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struct {
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/** out_w1tc : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
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* GPIO24 output.\\
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* 0: Not clear\\
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* 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to clear GPIO_OUT_REG. \\
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*/
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uint32_t out_w1tc:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_out_w1tc_reg_t;
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/** Type of enable register
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* GPIO output enable register
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*/
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typedef union {
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struct {
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/** enable_data : R/W/WTC; bitpos: [28:0]; default: 0;
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* Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\
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* 0: Not enable\\
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* 1: Enable\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
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*/
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uint32_t enable_data:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_enable_reg_t;
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/** Type of enable_w1ts register
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* GPIO output enable set register
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*/
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typedef union {
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struct {
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/** enable_w1ts : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to set the output enable register GPIO_ENABLE_REG of
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* GPIO0 ~ GPIO24.\\
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* 0: Not set\\
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* 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to set GPIO_ENABLE_REG.\\
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*/
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uint32_t enable_w1ts:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_enable_w1ts_reg_t;
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/** Type of enable_w1tc register
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* GPIO output enable clear register
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*/
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typedef union {
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struct {
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/** enable_w1tc : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
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* GPIO0 ~ GPIO24. \\
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* 0: Not clear\\
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* 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to clear GPIO_ENABLE_REG.\\
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*/
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uint32_t enable_w1tc:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_enable_w1tc_reg_t;
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/** Type of in register
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* GPIO input register
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*/
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typedef union {
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struct {
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/** in_data_next : RO; bitpos: [28:0]; default: 0;
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* Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input
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* value:\\
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* 0: Low level\\
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* 1: High level\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
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*/
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uint32_t in_data_next:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_in_reg_t;
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/** Group: Interrupt Status Registers */
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/** Type of status register
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* GPIO interrupt status register
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*/
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typedef union {
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struct {
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/** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0;
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* The interrupt status of GPIO0 ~ GPIO24, can be configured by the software.
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*
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* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
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* - Each bit represents the status of its corresponding GPIO:
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*
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* - 0: Represents the GPIO does not generate the interrupt configured by
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* GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
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* - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
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* or this bit is configured to 1 by the software.
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*
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*/
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uint32_t status_interrupt:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_reg_t;
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/** Type of status_w1ts register
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* GPIO interrupt status set register
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*/
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typedef union {
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struct {
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/** status_w1ts : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to set the interrupt status register
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* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
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*
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* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
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* register to set GPIO_STATUS_INTERRUPT.
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*/
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uint32_t status_w1ts:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_w1ts_reg_t;
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/** Type of status_w1tc register
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* GPIO interrupt status clear register
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*/
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typedef union {
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struct {
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/** status_w1tc : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to clear the interrupt status register
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* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
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*
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* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
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* register to clear GPIO_STATUS_INTERRUPT.
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*/
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uint32_t status_w1tc:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_w1tc_reg_t;
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/** Type of procpu_int register
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* CPU interrupt status register
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*/
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typedef union {
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struct {
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/** procpu_int : RO; bitpos: [28:0]; default: 0;
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* Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\
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* 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the
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* interrupt configured by GPIO_PIN$n_INT_TYPE.\\
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* 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
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* after the CPU interrupt is enabled.\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This
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* interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
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* enable signal (bit13 of GPIO_PIN$n_REG). \\
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*/
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uint32_t procpu_int:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_procpu_int_reg_t;
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/** Type of status_next register
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* GPIO interrupt source register
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*/
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typedef union {
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struct {
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/** status_interrupt_next : RO; bitpos: [28:0]; default: 0;
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* Represents the interrupt source signal of GPIO0 ~ GPIO24.\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each
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* bit represents:\\
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* 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\
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* 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\
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* The interrupt could be rising edge interrupt, falling edge interrupt, level
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* sensitive interrupt and any edge interrupt.\\
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*/
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uint32_t status_interrupt_next:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_next_reg_t;
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/** Group: Pin Configuration Registers */
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/** Type of pinn register
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* GPIOn configuration register
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*/
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typedef union {
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struct {
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/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the second-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync2_bypass:2;
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/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
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* Configures to select pin drive mode. \\
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* 0: Normal output\\
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* 1: Open drain output \\
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*/
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uint32_t pinn_pad_driver:1;
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/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the first-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync1_bypass:2;
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uint32_t reserved_5:2;
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/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
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* Configures GPIO interrupt type.\\
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* 0: GPIO interrupt disabled\\
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* 1: Rising edge trigger\\
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* 2: Falling edge trigger\\
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* 3: Any edge trigger\\
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* 4: Low level trigger\\
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* 5: High level trigger\\
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*/
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uint32_t pinn_int_type:3;
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/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
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* Configures whether or not to enable GPIO wake-up function.\\
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* 0: Disable\\
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* 1: Enable\\
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* This function only wakes up the CPU from Light-sleep. \\
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*/
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uint32_t pinn_wakeup_enable:1;
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uint32_t reserved_11:2;
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/** pinn_int_ena : R/W; bitpos: [17:13]; default: 0;
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* Configures whether or not to enable CPU interrupt.
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*
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* - bit13: Configures whether or not to enable CPU interrupt:\\
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* 0: Disable\\
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* 1: Enable\\
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* - bit14 ~ bit17: invalid
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*/
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uint32_t pinn_int_ena:5;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} gpio_pinn_reg_t;
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/** Type of pin25 register
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* GPIO25 configuration register
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*/
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typedef union {
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struct {
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/** pin25_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the second-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pin25_sync2_bypass:2;
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/** pin25_pad_driver : R/W; bitpos: [2]; default: 0;
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* Configures to select pin drive mode. \\
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* 0: Normal output\\
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* 1: Open drain output \\
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*/
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uint32_t pin25_pad_driver:1;
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/** pin25_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the first-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pin25_sync1_bypass:2;
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uint32_t reserved_5:2;
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/** pin25_int_type : R/W; bitpos: [9:7]; default: 0;
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* Configures GPIO interrupt type.\\
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* 0: GPIO interrupt disabled\\
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* 1: Rising edge trigger\\
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* 2: Falling edge trigger\\
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* 3: Any edge trigger\\
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* 4: Low level trigger\\
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* 5: High level trigger\\
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*/
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uint32_t pin25_int_type:3;
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/** pin25_wakeup_enable : R/W; bitpos: [10]; default: 0;
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* Configures whether or not to enable GPIO wake-up function.\\
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* 0: Disable\\
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* 1: Enable\\
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* This function only wakes up the CPU from Light-sleep. \\
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*/
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uint32_t pin25_wakeup_enable:1;
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uint32_t reserved_11:2;
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/** pin25_int_ena : R/W; bitpos: [17:13]; default: 0;
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* Configures whether or not to enable CPU interrupt.
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*
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* - bit13: Configures whether or not to enable CPU interrupt:\\
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* 0: Disable\\
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* 1: Enable\\
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* - bit14 ~ bit17: invalid
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*/
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uint32_t pin25_int_ena:5;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} gpio_pin25_reg_t;
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/** Type of pin26 register
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* GPIO26 configuration register
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*/
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typedef union {
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struct {
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/** pin26_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the second-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pin26_sync2_bypass:2;
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/** pin26_pad_driver : R/W; bitpos: [2]; default: 0;
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* Configures to select pin drive mode. \\
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* 0: Normal output\\
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* 1: Open drain output \\
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*/
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uint32_t pin26_pad_driver:1;
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/** pin26_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the first-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pin26_sync1_bypass:2;
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uint32_t reserved_5:2;
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/** pin26_int_type : R/W; bitpos: [9:7]; default: 0;
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* Configures GPIO interrupt type.\\
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* 0: GPIO interrupt disabled\\
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* 1: Rising edge trigger\\
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* 2: Falling edge trigger\\
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* 3: Any edge trigger\\
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* 4: Low level trigger\\
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* 5: High level trigger\\
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*/
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uint32_t pin26_int_type:3;
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/** pin26_wakeup_enable : R/W; bitpos: [10]; default: 0;
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* Configures whether or not to enable GPIO wake-up function.\\
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* 0: Disable\\
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* 1: Enable\\
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* This function only wakes up the CPU from Light-sleep. \\
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*/
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uint32_t pin26_wakeup_enable:1;
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uint32_t reserved_11:2;
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/** pin26_int_ena : R/W; bitpos: [17:13]; default: 0;
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* Configures whether or not to enable CPU interrupt.
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*
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* - bit13: Configures whether or not to enable CPU interrupt:\\
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* 0: Disable\\
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* 1: Enable\\
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* - bit14 ~ bit17: invalid
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*/
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uint32_t pin26_int_ena:5;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} gpio_pin26_reg_t;
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/** Type of pin27 register
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* GPIO27 configuration register
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*/
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typedef union {
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struct {
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/** pin27_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the second-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pin27_sync2_bypass:2;
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/** pin27_pad_driver : R/W; bitpos: [2]; default: 0;
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* Configures to select pin drive mode. \\
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* 0: Normal output\\
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* 1: Open drain output \\
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*/
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uint32_t pin27_pad_driver:1;
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/** pin27_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
|
|
* operating clock for the first-level synchronization.\\
|
|
* 0: Not synchronize\\
|
|
* 1: Synchronize on falling edge\\
|
|
* 2: Synchronize on rising edge\\
|
|
* 3: Synchronize on rising edge\\
|
|
*/
|
|
uint32_t pin27_sync1_bypass:2;
|
|
uint32_t reserved_5:2;
|
|
/** pin27_int_type : R/W; bitpos: [9:7]; default: 0;
|
|
* Configures GPIO interrupt type.\\
|
|
* 0: GPIO interrupt disabled\\
|
|
* 1: Rising edge trigger\\
|
|
* 2: Falling edge trigger\\
|
|
* 3: Any edge trigger\\
|
|
* 4: Low level trigger\\
|
|
* 5: High level trigger\\
|
|
*/
|
|
uint32_t pin27_int_type:3;
|
|
/** pin27_wakeup_enable : R/W; bitpos: [10]; default: 0;
|
|
* Configures whether or not to enable GPIO wake-up function.\\
|
|
* 0: Disable\\
|
|
* 1: Enable\\
|
|
* This function only wakes up the CPU from Light-sleep. \\
|
|
*/
|
|
uint32_t pin27_wakeup_enable:1;
|
|
uint32_t reserved_11:2;
|
|
/** pin27_int_ena : R/W; bitpos: [17:13]; default: 0;
|
|
* Configures whether or not to enable CPU interrupt.
|
|
*
|
|
* - bit13: Configures whether or not to enable CPU interrupt:\\
|
|
* 0: Disable\\
|
|
* 1: Enable\\
|
|
* - bit14 ~ bit17: invalid
|
|
*/
|
|
uint32_t pin27_int_ena:5;
|
|
uint32_t reserved_18:14;
|
|
};
|
|
uint32_t val;
|
|
} gpio_pin27_reg_t;
|
|
|
|
/** Type of pin28 register
|
|
* GPIO28 configuration register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** pin28_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
|
|
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
|
|
* operating clock for the second-level synchronization.\\
|
|
* 0: Not synchronize\\
|
|
* 1: Synchronize on falling edge\\
|
|
* 2: Synchronize on rising edge\\
|
|
* 3: Synchronize on rising edge\\
|
|
*/
|
|
uint32_t pin28_sync2_bypass:2;
|
|
/** pin28_pad_driver : R/W; bitpos: [2]; default: 0;
|
|
* Configures to select pin drive mode. \\
|
|
* 0: Normal output\\
|
|
* 1: Open drain output \\
|
|
*/
|
|
uint32_t pin28_pad_driver:1;
|
|
/** pin28_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
|
|
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
|
|
* operating clock for the first-level synchronization.\\
|
|
* 0: Not synchronize\\
|
|
* 1: Synchronize on falling edge\\
|
|
* 2: Synchronize on rising edge\\
|
|
* 3: Synchronize on rising edge\\
|
|
*/
|
|
uint32_t pin28_sync1_bypass:2;
|
|
uint32_t reserved_5:2;
|
|
/** pin28_int_type : R/W; bitpos: [9:7]; default: 0;
|
|
* Configures GPIO interrupt type.\\
|
|
* 0: GPIO interrupt disabled\\
|
|
* 1: Rising edge trigger\\
|
|
* 2: Falling edge trigger\\
|
|
* 3: Any edge trigger\\
|
|
* 4: Low level trigger\\
|
|
* 5: High level trigger\\
|
|
*/
|
|
uint32_t pin28_int_type:3;
|
|
/** pin28_wakeup_enable : R/W; bitpos: [10]; default: 0;
|
|
* Configures whether or not to enable GPIO wake-up function.\\
|
|
* 0: Disable\\
|
|
* 1: Enable\\
|
|
* This function only wakes up the CPU from Light-sleep. \\
|
|
*/
|
|
uint32_t pin28_wakeup_enable:1;
|
|
uint32_t reserved_11:2;
|
|
/** pin28_int_ena : R/W; bitpos: [17:13]; default: 0;
|
|
* Configures whether or not to enable CPU interrupt.
|
|
*
|
|
* - bit13: Configures whether or not to enable CPU interrupt:\\
|
|
* 0: Disable\\
|
|
* 1: Enable\\
|
|
* - bit14 ~ bit17: invalid
|
|
*/
|
|
uint32_t pin28_int_ena:5;
|
|
uint32_t reserved_18:14;
|
|
};
|
|
uint32_t val;
|
|
} gpio_pin28_reg_t;
|
|
|
|
|
|
/** Group: Input Configuration Registers */
|
|
/** Type of func0_in_sel_cfg register
|
|
* Configuration register for input signal 0
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** func_in_sel : R/W; bitpos: [5:0]; default: 48;
|
|
* Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\
|
|
* 0: Select GPIO0\\
|
|
* 1: Select GPIO1\\
|
|
* ......\\
|
|
* 23: Select GPIO23\\
|
|
* 24: Select GPIO24\\
|
|
* Or\\
|
|
* 0x20: A constantly high input\\
|
|
* 0x30: A constantly low input\\
|
|
*/
|
|
uint32_t func_in_sel:6;
|
|
/** func_in_inv_sel : R/W; bitpos: [6]; default: 0;
|
|
* Configures whether or not to invert the input value.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func_in_inv_sel:1;
|
|
/** sig_in_sel : R/W; bitpos: [7]; default: 0;
|
|
* Configures whether or not to route signals via GPIO matrix.\\
|
|
* 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
|
|
* IO MUX.\\
|
|
* 1: Route signals via GPIO matrix.\\
|
|
*/
|
|
uint32_t sig_in_sel:1;
|
|
uint32_t reserved_8:24;
|
|
};
|
|
uint32_t val;
|
|
} gpio_func_in_sel_cfg_reg_t;
|
|
|
|
/** Group: Output Configuration Registers */
|
|
/** Type of funcn_out_sel_cfg register
|
|
* Configuration register for GPIOn output
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
|
|
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
|
|
* output from GPIOn.\\
|
|
* 0: Select signal 0\\
|
|
* 1: Select signal 1\\
|
|
* ......\\
|
|
* 254: Select signal 254\\
|
|
* 255: Select signal 255\\
|
|
* Or\\
|
|
* 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
|
|
* output enable.
|
|
*
|
|
* For the detailed signal list, see Table <a
|
|
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
|
|
* "
|
|
*/
|
|
uint32_t funcn_out_sel:9;
|
|
/** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
|
|
* Configures whether or not to invert the output value.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t funcn_out_inv_sel:1;
|
|
/** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
|
|
* Configures to select the source of output enable signal.\\
|
|
* 0: Use output enable signal from peripheral.\\
|
|
* 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\
|
|
*/
|
|
uint32_t funcn_oe_sel:1;
|
|
/** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to invert the output enable signal.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t funcn_oe_inv_sel:1;
|
|
uint32_t reserved_12:20;
|
|
};
|
|
uint32_t val;
|
|
} gpio_funcn_out_sel_cfg_reg_t;
|
|
|
|
/** Type of func25_out_sel_cfg register
|
|
* Configuration register for GPIO$n output
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** func25_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
|
|
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
|
|
* output from GPIO$n.\\
|
|
* 0: Select signal 0\\
|
|
* 1: Select signal 1\\
|
|
* ......\\
|
|
* 254: Select signal 254\\
|
|
* 255: Select signal 255\\
|
|
* Or\\
|
|
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
|
|
* and output enable.
|
|
*
|
|
* For the detailed signal list, see Table <a
|
|
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
|
|
* "
|
|
*/
|
|
uint32_t func25_out_sel:9;
|
|
/** func25_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
|
|
* Configures whether or not to invert the output value.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func25_out_inv_sel:1;
|
|
/** func25_oe_sel : R/W; bitpos: [10]; default: 0;
|
|
* Configures to select the source of output enable signal.\\
|
|
* 0: Use output enable signal from peripheral.\\
|
|
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
|
|
*/
|
|
uint32_t func25_oe_sel:1;
|
|
/** func25_oe_inv_sel : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to invert the output enable signal.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func25_oe_inv_sel:1;
|
|
uint32_t reserved_12:20;
|
|
};
|
|
uint32_t val;
|
|
} gpio_func25_out_sel_cfg_reg_t;
|
|
|
|
/** Type of func26_out_sel_cfg register
|
|
* Configuration register for GPIO$n output
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** func26_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
|
|
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
|
|
* output from GPIO$n.\\
|
|
* 0: Select signal 0\\
|
|
* 1: Select signal 1\\
|
|
* ......\\
|
|
* 254: Select signal 254\\
|
|
* 255: Select signal 255\\
|
|
* Or\\
|
|
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
|
|
* and output enable.
|
|
*
|
|
* For the detailed signal list, see Table <a
|
|
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
|
|
* "
|
|
*/
|
|
uint32_t func26_out_sel:9;
|
|
/** func26_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
|
|
* Configures whether or not to invert the output value.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func26_out_inv_sel:1;
|
|
/** func26_oe_sel : R/W; bitpos: [10]; default: 0;
|
|
* Configures to select the source of output enable signal.\\
|
|
* 0: Use output enable signal from peripheral.\\
|
|
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
|
|
*/
|
|
uint32_t func26_oe_sel:1;
|
|
/** func26_oe_inv_sel : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to invert the output enable signal.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func26_oe_inv_sel:1;
|
|
uint32_t reserved_12:20;
|
|
};
|
|
uint32_t val;
|
|
} gpio_func26_out_sel_cfg_reg_t;
|
|
|
|
/** Type of func27_out_sel_cfg register
|
|
* Configuration register for GPIO$n output
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** func27_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
|
|
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
|
|
* output from GPIO$n.\\
|
|
* 0: Select signal 0\\
|
|
* 1: Select signal 1\\
|
|
* ......\\
|
|
* 254: Select signal 254\\
|
|
* 255: Select signal 255\\
|
|
* Or\\
|
|
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
|
|
* and output enable.
|
|
*
|
|
* For the detailed signal list, see Table <a
|
|
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
|
|
* "
|
|
*/
|
|
uint32_t func27_out_sel:9;
|
|
/** func27_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
|
|
* Configures whether or not to invert the output value.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func27_out_inv_sel:1;
|
|
/** func27_oe_sel : R/W; bitpos: [10]; default: 0;
|
|
* Configures to select the source of output enable signal.\\
|
|
* 0: Use output enable signal from peripheral.\\
|
|
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
|
|
*/
|
|
uint32_t func27_oe_sel:1;
|
|
/** func27_oe_inv_sel : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to invert the output enable signal.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func27_oe_inv_sel:1;
|
|
uint32_t reserved_12:20;
|
|
};
|
|
uint32_t val;
|
|
} gpio_func27_out_sel_cfg_reg_t;
|
|
|
|
/** Type of func28_out_sel_cfg register
|
|
* Configuration register for GPIO$n output
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** func28_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
|
|
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
|
|
* output from GPIO$n.\\
|
|
* 0: Select signal 0\\
|
|
* 1: Select signal 1\\
|
|
* ......\\
|
|
* 254: Select signal 254\\
|
|
* 255: Select signal 255\\
|
|
* Or\\
|
|
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
|
|
* and output enable.
|
|
*
|
|
* For the detailed signal list, see Table <a
|
|
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
|
|
* "
|
|
*/
|
|
uint32_t func28_out_sel:9;
|
|
/** func28_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
|
|
* Configures whether or not to invert the output value.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func28_out_inv_sel:1;
|
|
/** func28_oe_sel : R/W; bitpos: [10]; default: 0;
|
|
* Configures to select the source of output enable signal.\\
|
|
* 0: Use output enable signal from peripheral.\\
|
|
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
|
|
*/
|
|
uint32_t func28_oe_sel:1;
|
|
/** func28_oe_inv_sel : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to invert the output enable signal.\\
|
|
* 0: Not invert\\
|
|
* 1: Invert\\
|
|
*/
|
|
uint32_t func28_oe_inv_sel:1;
|
|
uint32_t reserved_12:20;
|
|
};
|
|
uint32_t val;
|
|
} gpio_func28_out_sel_cfg_reg_t;
|
|
|
|
|
|
/** Group: Clock Gate Register */
|
|
/** Type of clock_gate register
|
|
* GPIO clock gate register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** clk_en : R/W; bitpos: [0]; default: 1;
|
|
* Configures whether or not to enable clock gate.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable, the clock is free running. \\
|
|
*/
|
|
uint32_t clk_en:1;
|
|
uint32_t reserved_1:31;
|
|
};
|
|
uint32_t val;
|
|
} gpio_clock_gate_reg_t;
|
|
|
|
|
|
/** Group: Version Register */
|
|
/** Type of date register
|
|
* GPIO version register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** date : R/W; bitpos: [27:0]; default: 37753392;
|
|
* Version control register. \\
|
|
*/
|
|
uint32_t date:28;
|
|
uint32_t reserved_28:4;
|
|
};
|
|
uint32_t val;
|
|
} gpio_date_reg_t;
|
|
|
|
|
|
typedef struct {
|
|
volatile gpio_strap_reg_t strap;
|
|
volatile gpio_out_reg_t out;
|
|
volatile gpio_out_w1ts_reg_t out_w1ts;
|
|
volatile gpio_out_w1tc_reg_t out_w1tc;
|
|
uint32_t reserved_010[9];
|
|
volatile gpio_enable_reg_t enable;
|
|
volatile gpio_enable_w1ts_reg_t enable_w1ts;
|
|
volatile gpio_enable_w1tc_reg_t enable_w1tc;
|
|
uint32_t reserved_040[9];
|
|
volatile gpio_in_reg_t in;
|
|
uint32_t reserved_068[3];
|
|
volatile gpio_status_reg_t status;
|
|
volatile gpio_status_w1ts_reg_t status_w1ts;
|
|
volatile gpio_status_w1tc_reg_t status_w1tc;
|
|
uint32_t reserved_080[9];
|
|
volatile gpio_procpu_int_reg_t procpu_int;
|
|
uint32_t reserved_0a8[3];
|
|
volatile gpio_status_next_reg_t status_next;
|
|
uint32_t reserved_0b8[3];
|
|
volatile gpio_pinn_reg_t pinn[25];
|
|
volatile gpio_pin25_reg_t pin25;
|
|
volatile gpio_pin26_reg_t pin26;
|
|
volatile gpio_pin27_reg_t pin27;
|
|
volatile gpio_pin28_reg_t pin28;
|
|
uint32_t reserved_138[99];
|
|
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
|
|
uint32_t reserved_4ac[256];
|
|
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25];
|
|
volatile gpio_func25_out_sel_cfg_reg_t func25_out_sel_cfg;
|
|
volatile gpio_func26_out_sel_cfg_reg_t func26_out_sel_cfg;
|
|
volatile gpio_func27_out_sel_cfg_reg_t func27_out_sel_cfg;
|
|
volatile gpio_func28_out_sel_cfg_reg_t func28_out_sel_cfg;
|
|
uint32_t reserved_b38[176];
|
|
volatile gpio_clock_gate_reg_t clock_gate;
|
|
volatile gpio_date_reg_t date;
|
|
} gpio_dev_t;
|
|
|
|
extern gpio_dev_t GPIO;
|
|
|
|
#ifndef __cplusplus
|
|
_Static_assert(sizeof(gpio_dev_t) == 0xe00, "Invalid size of gpio_dev_t structure");
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|