mirror of
https://github.com/espressif/esp-idf.git
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209 lines
6.7 KiB
C
209 lines
6.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_types.h>
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_check.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/adc_private.h"
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#include "driver/gpio.h"
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#include "hal/adc_hal.h"
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#include "hal/adc_hal_common.h"
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#include "hal/adc_hal_conf.h"
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#include "soc/adc_periph.h"
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//For calibration
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp_efuse_rtc_table.h"
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#elif SOC_ADC_CALIBRATION_V1_SUPPORTED
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#include "esp_efuse_rtc_calib.h"
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#endif
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static const char *TAG = "adc_common";
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static portMUX_TYPE s_spinlock = portMUX_INITIALIZER_UNLOCKED;
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extern portMUX_TYPE rtc_spinlock;
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/*------------------------------------------------------------------------------
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* For those who use APB_SARADC periph
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*----------------------------------------------------------------------------*/
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static int s_adc_digi_ctrlr_cnt;
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void adc_apb_periph_claim(void)
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{
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portENTER_CRITICAL(&s_spinlock);
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s_adc_digi_ctrlr_cnt++;
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if (s_adc_digi_ctrlr_cnt == 1) {
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//enable ADC digital part
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periph_module_enable(PERIPH_SARADC_MODULE);
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//reset ADC digital part
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periph_module_reset(PERIPH_SARADC_MODULE);
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}
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portEXIT_CRITICAL(&s_spinlock);
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}
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void adc_apb_periph_free(void)
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{
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portENTER_CRITICAL(&s_spinlock);
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s_adc_digi_ctrlr_cnt--;
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if (s_adc_digi_ctrlr_cnt == 0) {
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periph_module_disable(PERIPH_SARADC_MODULE);
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} else if (s_adc_digi_ctrlr_cnt < 0) {
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portEXIT_CRITICAL(&s_spinlock);
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ESP_LOGE(TAG, "%s called, but `s_adc_digi_ctrlr_cnt == 0`", __func__);
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abort();
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}
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portEXIT_CRITICAL(&s_spinlock);
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}
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/*------------------------------------------------------------------------------
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* ADC Power
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*----------------------------------------------------------------------------*/
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// This gets incremented when adc_power_acquire() is called, and decremented when
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// adc_power_release() is called. ADC is powered down when the value reaches zero.
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// Should be modified within critical section (ADC_ENTER/EXIT_CRITICAL).
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static int s_adc_power_on_cnt;
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static void adc_power_on_internal(void)
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{
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/* Set the power always on to increase precision. */
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adc_hal_set_power_manage(ADC_POWER_SW_ON);
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}
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void adc_power_acquire(void)
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{
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portENTER_CRITICAL(&rtc_spinlock);
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s_adc_power_on_cnt++;
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if (s_adc_power_on_cnt == 1) {
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adc_power_on_internal();
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}
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portEXIT_CRITICAL(&rtc_spinlock);
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}
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static void adc_power_off_internal(void)
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{
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#if CONFIG_IDF_TARGET_ESP32
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adc_hal_set_power_manage(ADC_POWER_SW_OFF);
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#else
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adc_hal_set_power_manage(ADC_POWER_BY_FSM);
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#endif
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}
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void adc_power_release(void)
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{
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portENTER_CRITICAL(&rtc_spinlock);
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s_adc_power_on_cnt--;
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/* Sanity check */
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if (s_adc_power_on_cnt < 0) {
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portEXIT_CRITICAL(&rtc_spinlock);
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ESP_LOGE(TAG, "%s called, but s_adc_power_on_cnt == 0", __func__);
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abort();
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} else if (s_adc_power_on_cnt == 0) {
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adc_power_off_internal();
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}
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portEXIT_CRITICAL(&rtc_spinlock);
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}
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/*---------------------------------------------------------------
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ADC IOs
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---------------------------------------------------------------*/
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esp_err_t adc_io_to_channel(int io_num, adc_unit_t *unit_id, adc_channel_t *channel)
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{
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ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(io_num), ESP_ERR_INVALID_ARG, TAG, "invalid gpio number");
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ESP_RETURN_ON_FALSE(unit_id && channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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bool found = false;
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for (int i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
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for (int j = 0; j < SOC_ADC_MAX_CHANNEL_NUM; j++) {
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if (adc_channel_io_map[i][j] == io_num) {
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*channel = j;
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*unit_id = i;
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found = true;
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}
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}
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}
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return (found) ? ESP_OK : ESP_ERR_NOT_FOUND;
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}
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esp_err_t adc_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int *io_num)
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{
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ESP_RETURN_ON_FALSE(unit_id < SOC_ADC_PERIPH_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid unit");
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ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(unit_id), ESP_ERR_INVALID_ARG, TAG, "invalid channel");
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ESP_RETURN_ON_FALSE(io_num, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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*io_num = adc_channel_io_map[unit_id][channel];
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return ESP_OK;
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}
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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/*---------------------------------------------------------------
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ADC Hardware Calibration
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---------------------------------------------------------------*/
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#if CONFIG_IDF_TARGET_ESP32S2
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#define esp_efuse_rtc_calib_get_ver() esp_efuse_rtc_table_read_calib_version()
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static inline uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
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{
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int tag = esp_efuse_rtc_table_get_tag(version, adc_unit + 1, atten, RTCCALIB_V2_PARAM_VINIT);
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return esp_efuse_rtc_table_get_parsed_efuse_value(tag, false);
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}
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#endif
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static uint32_t s_adc_cali_param[SOC_ADC_PERIPH_NUM][SOC_ADC_ATTEN_NUM] = {};
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void adc_calc_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten)
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{
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if (s_adc_cali_param[adc_n][atten]) {
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ESP_EARLY_LOGV(TAG, "Use calibrated val ADC%d atten=%d: %04X", adc_n + 1, atten, s_adc_cali_param[adc_n][atten]);
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return ;
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}
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// check if we can fetch the values from eFuse.
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int version = esp_efuse_rtc_calib_get_ver();
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uint32_t init_code = 0;
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if (version == ESP_EFUSE_ADC_CALIB_VER) {
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init_code = esp_efuse_rtc_calib_get_init_code(version, adc_n, atten);
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} else {
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ESP_EARLY_LOGD(TAG, "Calibration eFuse is not configured, use self-calibration for ICode");
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adc_power_acquire();
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portENTER_CRITICAL(&rtc_spinlock);
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adc_ll_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
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const bool internal_gnd = true;
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init_code = adc_hal_self_calibration(adc_n, atten, internal_gnd);
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portEXIT_CRITICAL(&rtc_spinlock);
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adc_power_release();
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}
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s_adc_cali_param[adc_n][atten] = init_code;
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ESP_EARLY_LOGV(TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n + 1, atten, init_code);
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}
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void IRAM_ATTR adc_set_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten)
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{
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adc_hal_set_calibration_param(adc_n, s_adc_cali_param[adc_n][atten]);
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}
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static __attribute__((constructor)) void adc_hw_calibration(void)
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{
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//Calculate all ICode
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for (int i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
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adc_hal_calibration_init(i);
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for (int j = 0; j < SOC_ADC_ATTEN_NUM; j++) {
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/**
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* This may get wrong when attenuations are NOT consecutive on some chips,
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* update this when bringing up the calibration on that chip
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*/
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adc_calc_hw_calibration_code(i, j);
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}
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}
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}
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#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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