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5c30cc24fd
There are a bunch of cases you might want some pins not exposed. Eg. * Reading say 8 bit data and outputting the top 5 bits, discarding the rest by not mapping those data pins to output pins * Not using hsync/vsync because sync data is embedded within the data bits for more timing flexibility (eg. interlacing). * Using the LCD module as a high speed parallel data output bus, with no need for sync/control pins. Removing this validation makes these cases work. Merges https://github.com/espressif/esp-idf/pull/13103 |
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