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https://github.com/espressif/esp-idf.git
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5b54ae76d4
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:
1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.
For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.
This introduced two possible issues:
1. Overflow when multiplying systimer counter by 5
- Should not be an issue, since systimer counter is 52-bit, so
counter * 5 is no more than 55-bit.
2. The code needs to perform:
- divide by 5: when converting from microseconds to ticks
- divide by 52: when converting from ticks to microseconds
The latter potentially introduces a performance issue for the
esp_timer_get_time function.
372 lines
17 KiB
C
372 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The long term plan is to have a single soc_caps.h for each peripheral.
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// During the refactoring and multichip support development process, we
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// seperate these information into periph_caps.h for each peripheral and
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// include them here.
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/*
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* These defines are parsed and imported as kconfig variables via the script
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* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
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*
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* If this file is changed the script will automatically run the script
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* and generate the kconfig variables as part of the pre-commit hooks.
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*
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* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c3/include/soc/'`
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*
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* For more information see `tools/gen_soc_caps_kconfig/README.md`
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*
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*/
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#pragma once
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_ADC_SUPPORTED 1
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#define SOC_DEDICATED_GPIO_SUPPORTED 1
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#define SOC_GDMA_SUPPORTED 1
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#define SOC_TWAI_SUPPORTED 1
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#define SOC_BT_SUPPORTED 1
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#define SOC_ASYNC_MEMCPY_SUPPORTED 1
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#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
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#define SOC_TEMP_SENSOR_SUPPORTED 1
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#define SOC_XT_WDT_SUPPORTED 1
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#define SOC_WIFI_SUPPORTED 1
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#define SOC_SUPPORTS_SECURE_DL_MODE 1
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#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
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#define SOC_EFUSE_HAS_EFUSE_RST_BUG 1
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#define SOC_RTC_FAST_MEM_SUPPORTED 1
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#define SOC_I2S_SUPPORTED 1
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#define SOC_RMT_SUPPORTED 1
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#define SOC_SIGMADELTA_SUPPORTED 1
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#define SOC_SUPPORT_COEXISTENCE 1
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#define SOC_AES_SUPPORTED 1
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#define SOC_MPI_SUPPORTED 1
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#define SOC_SHA_SUPPORTED 1
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#define SOC_HMAC_SUPPORTED 1
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#define SOC_DIG_SIGN_SUPPORTED 1
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#define SOC_FLASH_ENC_SUPPORTED 1
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/* Secure boot is only supported in ESP32-C3 revision > ECO3. We check ECO revision in
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* bootloader "security" configuration and accordingly prevent its usage for ECO2 and
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* earlier revisions */
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#define SOC_SECURE_BOOT_SUPPORTED 1
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#define SOC_MEMPROT_SUPPORTED 1
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_DMA (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_AES_GDMA (1)
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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/*-------------------------- ADC CAPS -------------------------------*/
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/*!< SAR ADC Module*/
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#define SOC_ADC_DIG_CTRL_SUPPORTED 1
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#define SOC_ADC_ARBITER_SUPPORTED 1
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#define SOC_ADC_FILTER_SUPPORTED 1
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#define SOC_ADC_MONITOR_SUPPORTED 1
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#define SOC_ADC_PERIPH_NUM (2)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
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#define SOC_ADC_MAX_CHANNEL_NUM (5)
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#define SOC_ADC_ATTEN_NUM (4)
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/*!< Digital */
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#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
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#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
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#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
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#define SOC_ADC_DIGI_FILTER_NUM (2)
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#define SOC_ADC_DIGI_MONITOR_NUM (2)
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/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
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/*!< RTC */
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#define SOC_ADC_RTC_MIN_BITWIDTH (12)
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#define SOC_ADC_RTC_MAX_BITWIDTH (12)
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/*!< Calibration */
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#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (1)
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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/*-------------------------- CACHE CAPS --------------------------------------*/
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#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
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#define SOC_CACHE_MEMORY_IBANK_SIZE 0x4000 // has to be same as the definition in ROM component
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/*-------------------------- CPU CAPS ----------------------------------------*/
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#define SOC_CPU_CORES_NUM (1U)
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#define SOC_CPU_INTR_NUM 32
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#define SOC_CPU_HAS_FLEXIBLE_INTC 1
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#define SOC_CPU_BREAKPOINTS_NUM 8
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#define SOC_CPU_WATCHPOINTS_NUM 8
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#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
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/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
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/** The maximum length of a Digital Signature in bits. */
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#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
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/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
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#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
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/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
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See TRM DS chapter for more details */
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#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
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/*-------------------------- GDMA CAPS -------------------------------------*/
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#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
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#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
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#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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// ESP32-C3 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1U)
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#define SOC_GPIO_PIN_COUNT (22)
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// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
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// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
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#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1)
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// Force hold is a new function of ESP32-C3
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#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
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// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
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#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
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#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
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#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
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// Support to configure sleep status
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#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
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/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
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#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
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#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
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#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
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/*-------------------------- I2C CAPS ----------------------------------------*/
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// ESP32-C3 has 1 I2C
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#define SOC_I2C_NUM (1U)
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_SUPPORT_SLAVE (1)
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// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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#define SOC_I2C_SUPPORT_RTC (1)
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/*-------------------------- I2S CAPS ----------------------------------------*/
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#define SOC_I2S_NUM (1)
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#define SOC_I2S_HW_VERSION_2 (1)
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#define SOC_I2S_SUPPORTS_PCM (1)
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#define SOC_I2S_SUPPORTS_PDM (1)
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#define SOC_I2S_SUPPORTS_PDM_TX (1)
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#define SOC_I2S_SUPPORTS_PDM_CODEC (1)
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#define SOC_I2S_SUPPORTS_TDM (1)
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/*-------------------------- LEDC CAPS ---------------------------------------*/
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#define SOC_LEDC_SUPPORT_APB_CLOCK (1)
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#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
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#define SOC_LEDC_CHANNEL_NUM (6)
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#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
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#define SOC_LEDC_SUPPORT_FADE_STOP (1)
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/*-------------------------- MPU CAPS ----------------------------------------*/
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#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
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#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
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#define SOC_MPU_REGIONS_MAX_NUM 8
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#define SOC_MPU_REGION_RO_SUPPORTED 0
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#define SOC_MPU_REGION_WO_SUPPORTED 0
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/*--------------------------- RMT CAPS ---------------------------------------*/
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#define SOC_RMT_GROUPS 1U /*!< One RMT group */
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#define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
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#define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
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#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
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#define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
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#define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
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#define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
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#define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
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#define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
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#define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
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#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
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#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
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#define SOC_RMT_SUPPORT_APB 1 /*!< Support set APB as the RMT clock source */
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#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */
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/*-------------------------- RTC CAPS --------------------------------------*/
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#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
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#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
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#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
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#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
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#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
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#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
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* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
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#define SOC_RTCIO_PIN_COUNT (0U)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GDMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
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#define SOC_SIGMADELTA_NUM (1U) // 1 sigma-delta peripheral
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#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6
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#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
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#define SOC_SPI_SUPPORT_DDRCLK 1
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#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
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#define SOC_SPI_SUPPORT_CD_SIG 1
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#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
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#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
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// Peripheral supports output given level during its "dummy phase"
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
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#define SOC_MEMSPI_IS_INDEPENDENT 1
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#define SOC_SPI_MAX_PRE_DIVIDER 16
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/*-------------------------- SPI MEM CAPS ---------------------------------------*/
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#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
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#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
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#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
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#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
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#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_SUPPORTED 1
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#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
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#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
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#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
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#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us)
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#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
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#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
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/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
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#define SOC_TIMER_GROUPS (2)
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#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
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#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
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#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
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#define SOC_TIMER_GROUP_SUPPORT_APB (1)
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#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
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/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
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#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
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/*-------------------------- TWAI CAPS ---------------------------------------*/
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#define SOC_TWAI_BRP_MIN 2
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#define SOC_TWAI_BRP_MAX 16384
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#define SOC_TWAI_SUPPORTS_RX_STATUS 1
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_RSA 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
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#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
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/*-------------------------- Flash Encryption CAPS----------------------------*/
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#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
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/*-------------------------- MEMPROT CAPS ------------------------------------*/
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#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16
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#define SOC_MEMPROT_MEM_ALIGN_SIZE 512
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/*-------------------------- UART CAPS ---------------------------------------*/
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// ESP32-C3 has 2 UARTs
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#define SOC_UART_NUM (2)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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#define SOC_UART_SUPPORT_RTC_CLK (1)
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#define SOC_UART_SUPPORT_XTAL_CLK (1)
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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#define SOC_UART_REQUIRE_CORE_RESET (1)
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// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
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#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
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/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
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#define SOC_COEX_HW_PTI (1)
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/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
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#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
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#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
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/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
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#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
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/*-------------------------- Power Management CAPS ----------------------------*/
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#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
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#define SOC_PM_SUPPORT_BT_WAKEUP (1)
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#define SOC_PM_SUPPORT_CPU_PD (1)
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#define SOC_PM_SUPPORT_WIFI_PD (1)
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#define SOC_PM_SUPPORT_BT_PD (1)
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/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
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#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
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#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
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/*------------------------------------ WI-FI CAPS ------------------------------------*/
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#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
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#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */
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#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
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#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
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#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
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#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
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