esp-idf/components/esp_gdbstub
Mahavir Jain 9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-22 13:34:32 +08:00
..
include This commit add to GDBstup: 2022-03-01 19:49:24 +03:00
private_include refactor(freertos/task_snapshot): Make task snapshot private 2023-10-07 13:14:55 +08:00
src fix(soc): change debug addr range to CPU subsystem range 2024-01-22 13:34:32 +08:00
test_gdbstub_host esp_gdbstub: add tests for riscv jump instructions decoding 2023-05-19 20:15:58 +08:00
CMakeLists.txt refactor(linux): excluded all non-Linux components from build 2023-10-16 17:06:54 +08:00
Kconfig refactor(freertos): Remove option for Task Snapshot 2023-08-28 20:11:27 +08:00
linker.lf Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
sdkconfig.rename Docs: Add C3 support to build_docs 2020-12-28 12:25:03 +08:00