mirror of
https://github.com/espressif/esp-idf.git
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341 lines
13 KiB
C
341 lines
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "../esp_psram_impl.h"
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#include "rom/spi_flash.h"
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#include "rom/opi_flash.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "hal/gpio_hal.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "esp_private/esp_gpio_reserve.h"
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#include "hal/psram_ctrlr_ll.h"
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#include "esp_quad_psram_defs.h"
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#include "soc/soc_caps.h"
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static const char* TAG = "quad_psram";
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static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
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static void config_psram_spi_phases(void);
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static uint8_t s_psram_cs_io = (uint8_t) -1;
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uint8_t esp_psram_impl_get_cs_io(void)
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{
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return s_psram_cs_io;
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}
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void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation)
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{
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esp_rom_spiflash_read_mode_t rd_mode = (mode == PSRAM_HAL_CMD_QPI) ? ESP_ROM_SPIFLASH_QIO_MODE : ESP_ROM_SPIFLASH_SLOWRD_MODE;
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esp_rom_spi_set_op_mode(spi_num, rd_mode);
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if (mode == PSRAM_HAL_CMD_QPI) {
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psram_ctrlr_ll_enable_quad_command(PSRAM_CTRLR_LL_MSPI_ID_1, true);
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}
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psram_ctrlr_ll_common_transaction_base(spi_num, rd_mode,
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cmd, cmd_bit_len,
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addr, addr_bit_len,
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dummy_bits,
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mosi_data, mosi_bit_len,
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miso_data, miso_bit_len,
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cs_mask,
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is_write_erase_operation);
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}
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//exit QPI mode(set back to SPI mode)
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static void psram_disable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_QPI,
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PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//TODO IDF-4307
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//switch psram burst length(32 bytes or 1024 bytes)
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//datasheet says it should be 1024 bytes by default
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static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode)
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{
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psram_exec_cmd(spi_num, mode,
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PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//send reset command to psram, in spi mode
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static void psram_reset_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_RESET_EN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_RESET, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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esp_err_t psram_enable_wrap(uint32_t wrap_size)
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{
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//TODO: IDF-4307
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static uint32_t current_wrap_size = 0;
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if (current_wrap_size == wrap_size) {
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return ESP_OK;
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}
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switch (wrap_size) {
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case 32:
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case 0:
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psram_set_wrap_burst_length(1, PSRAM_HAL_CMD_QPI);
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current_wrap_size = wrap_size;
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return ESP_OK;
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case 16:
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case 64:
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default:
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return ESP_FAIL;
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}
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}
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bool psram_support_wrap_size(uint32_t wrap_size)
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{
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switch (wrap_size) {
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case 0:
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case 32:
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return true;
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case 16:
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case 64:
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default:
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return false;
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}
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}
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//Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
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static void psram_read_id(int spi_num, uint8_t* dev_id, int id_bits)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_DEVICE_ID, 8, /* command and command bit len*/
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0, 24, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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dev_id, id_bits, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//enter QPI mode
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static void psram_enable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
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PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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PSRAM_LL_CS_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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static void psram_set_cs_timing(void)
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{
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psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_HOLD_VAL);
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psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_SETUP_VAL);
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}
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static void psram_gpio_config(void)
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{
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//CS1
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uint8_t cs1_io = PSRAM_CS_IO;
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if (cs1_io == MSPI_IOMUX_PIN_NUM_CS1) {
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gpio_ll_func_sel(&GPIO, cs1_io, FUNC_SPICS1_SPICS1);
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} else {
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esp_rom_gpio_connect_out_signal(cs1_io, FSPICS1_OUT_IDX, 0, 0);
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gpio_ll_func_sel(&GPIO, cs1_io, PIN_FUNC_GPIO);
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}
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s_psram_cs_io = cs1_io;
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//WP HD
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uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
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#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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// MSPI pins (except wp / hd) are all configured via IO_MUX in 1st bootloader.
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} else {
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// MSPI pins (except wp / hd) are all configured via GPIO matrix in 1st bootloader.
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wp_io = esp_rom_efuse_get_flash_wp_gpio();
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}
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esp_rom_spiflash_select_qio_pins(wp_io, spiconfig);
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#else
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//This ROM function will init both WP and HD pins.
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esp_rom_spiflash_select_qio_pins(wp_io, 0);
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#endif
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// Reserve psram pins
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esp_gpio_reserve(BIT64(cs1_io) | BIT64(wp_io));
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}
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#if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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static void s_config_psram_clock(void)
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{
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// This function can be extended if we have other psram frequency
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uint32_t clock_conf = 0;
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#if (CONFIG_SPIRAM_SPEED == 80)
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clock_conf = psram_ctrlr_ll_calculate_clock_reg(1);
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#elif (CONFIG_SPIRAM_SPEED == 40)
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clock_conf = psram_ctrlr_ll_calculate_clock_reg(2);
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#endif
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psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_0, clock_conf);
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}
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#endif //#if !SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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/**
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* For certain wafer version and 8MB case, we consider it as 4MB mode as it uses 2T mode
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*/
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bool s_check_aps3204_2tmode(void)
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{
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uint64_t full_eid = 0;
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psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_EID_BITS_NUM);
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bool is_2t = false;
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uint32_t eid_47_16 = __builtin_bswap32((full_eid >> 16) & UINT32_MAX);
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ESP_EARLY_LOGD(TAG, "full_eid: 0x%" PRIx64", eid_47_16: 0x%"PRIx32", (eid_47_16 >> 5) & 0xfffff: 0x%"PRIx32, full_eid, eid_47_16, (eid_47_16 >> 5) & 0xfffff);
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if (((eid_47_16 >> 5) & 0xfffff) == 0x8a445) {
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is_2t = true;
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}
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return is_2t;
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}
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esp_err_t esp_psram_impl_enable(void)
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{
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psram_gpio_config();
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psram_set_cs_timing();
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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//enter MSPI slow mode to init PSRAM device registers
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mspi_timing_enter_low_speed_mode(true);
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#endif // SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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uint32_t psram_id = 0;
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//We use SPI1 to init PSRAM
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psram_disable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
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psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM);
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if (!PSRAM_IS_VALID(psram_id)) {
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/* 16Mbit psram ID read error workaround:
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* treat the first read id as a dummy one as the pre-condition,
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* Send Read ID command again
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*/
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psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM);
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if (!PSRAM_IS_VALID(psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)psram_id);
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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if (PSRAM_IS_64MBIT_TRIAL(psram_id)) {
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s_psram_size = PSRAM_SIZE_8MB;
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} else {
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uint8_t density = PSRAM_SIZE_ID(psram_id);
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s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB :
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density == 0x1 ? PSRAM_SIZE_4MB :
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density == 0x2 ? PSRAM_SIZE_8MB : 0;
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}
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if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_aps3204_2tmode()) {
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s_psram_size = PSRAM_SIZE_4MB;
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}
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//SPI1: send psram reset command
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psram_reset_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
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//SPI1: send QPI enable command
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psram_enable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
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#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
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//Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
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mspi_timing_psram_tuning();
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//Configure SPI0 PSRAM related SPI Phases
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config_psram_spi_phases();
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//Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
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mspi_timing_enter_high_speed_mode(true);
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#else
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s_config_psram_clock();
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//Configure SPI0 PSRAM related SPI Phases
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config_psram_spi_phases();
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#endif
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return ESP_OK;
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}
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//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
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static void config_psram_spi_phases(void)
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{
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psram_ctrlr_ll_set_read_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_HAL_CMD_QPI);
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psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_QUAD_WRITE);
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psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_FAST_READ_QUAD);
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psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_ADDR_LENGTH);
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psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_FAST_READ_QUAD_DUMMY);
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psram_ctrlr_ll_set_cs_pin(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_CS_ID_1);
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}
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/*---------------------------------------------------------------------------------
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* Following APIs are not required to be IRAM-Safe
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*
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* Consider moving these to another file if this kind of APIs grows dramatically
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*-------------------------------------------------------------------------------*/
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esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
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{
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if (!out_size_bytes) {
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return ESP_ERR_INVALID_ARG;
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}
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*out_size_bytes = s_psram_size;
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return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
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}
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/**
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* This function is to get the available physical psram size in bytes.
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*
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* When ECC is enabled, the available size will be reduced.
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* On S3 Quad PSRAM, ECC is not enabled for now.
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*/
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esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
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{
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if (!out_size_bytes) {
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return ESP_ERR_INVALID_ARG;
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}
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*out_size_bytes = s_psram_size;
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return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
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}
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