esp-idf/components/esp_hw_support/compare_set.c
Angus Gratton 420aef1ffe Updates for riscv support
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00

50 lines
1.5 KiB
C

// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/compare_set.h"
#include "soc/spinlock.h"
#include "soc/soc_caps.h"
#if __XTENSA__ && SOC_SPIRAM_SUPPORTED
static spinlock_t global_extram_lock = SPINLOCK_INITIALIZER;
void compare_and_set_extram(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
{
uint32_t intlevel, old_value;
__asm__ __volatile__ ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) "\n"
: "=r"(intlevel));
spinlock_acquire(&global_extram_lock, SPINLOCK_WAIT_FOREVER);
old_value = *addr;
if (old_value == compare) {
*addr = *set;
}
spinlock_release(&global_extram_lock);
__asm__ __volatile__ ("memw \n"
"wsr %0, ps\n"
:: "r"(intlevel));
*set = old_value;
}
#else // __XTENSA__ && SOC_SPIRAM_SUPPORTED
void compare_and_set_extram(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
{
compare_and_set_native(addr, compare, set);
}
#endif // endif