mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
197 lines
7.8 KiB
C
197 lines
7.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <stdlib.h>
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#include <sys/cdefs.h>
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#include "esp_log.h"
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#include "esp_check.h"
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#include "esp_eth_phy_802_3.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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static const char *TAG = "dm9051.phy";
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/***************Vendor Specific Register***************/
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/**
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* @brief DSCR(DAVICOM Specified Configuration Register)
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*
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*/
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typedef union {
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struct {
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uint32_t reserved1 : 1; /* Reserved */
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uint32_t sleep : 1; /* Set 1 to enable PHY into sleep mode */
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uint32_t mfpsc : 1; /* MII frame preamble suppression control bit */
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uint32_t smrst : 1; /* Set 1 to reset all state machines of PHY */
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uint32_t rpdctr_en : 1; /* Set 1 to enable automatic reduced power down */
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uint32_t reserved2 : 2; /* Reserved */
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uint32_t flink100 : 1; /* Force Good Link in 100Mbps */
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uint32_t reserved3 : 2; /* Reserved */
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uint32_t tx_fx : 1; /* 100BASE-TX or FX Mode Control */
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uint32_t reserved4 : 1; /* Reserved */
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uint32_t bp_adpok : 1; /* BYPASS ADPOK */
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uint32_t bp_align : 1; /* Bypass Symbol Alignment Function */
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uint32_t bp_scr : 1; /* Bypass Scrambler/Descrambler Function */
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uint32_t bp_4b5b : 1; /* Bypass 4B5B Encoding and 5B4B Decoding */
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};
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uint32_t val;
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} dscr_reg_t;
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#define ETH_PHY_DSCR_REG_ADDR (0x10)
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/**
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* @brief DSCSR(DAVICOM Specified Configuration and Status Register)
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*
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*/
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typedef union {
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struct {
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uint32_t anmb : 4; /* Auto-Negotiation Monitor Bits */
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uint32_t phy_addr : 5; /* PHY Address */
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uint32_t reserved : 3; /* Reserved */
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uint32_t hdx10 : 1; /* 10M Half-Duplex Operation Mode */
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uint32_t fdx10 : 1; /* 10M Full-Duplex Operation Mode */
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uint32_t hdx100 : 1; /* 100M Half-Duplex Operation Mode */
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uint32_t fdx100 : 1; /* 100M Full-Duplex Operation Mode */
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};
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uint32_t val;
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} dscsr_reg_t;
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#define ETH_PHY_DSCSR_REG_ADDR (0x11)
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typedef struct {
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phy_802_3_t phy_802_3;
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} phy_dm9051_t;
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static esp_err_t dm9051_update_link_duplex_speed(phy_dm9051_t *dm9051)
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{
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esp_err_t ret = ESP_OK;
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esp_eth_mediator_t *eth = dm9051->phy_802_3.eth;
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uint32_t addr = dm9051->phy_802_3.addr;
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eth_speed_t speed = ETH_SPEED_10M;
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eth_duplex_t duplex = ETH_DUPLEX_HALF;
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uint32_t peer_pause_ability = false;
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bmsr_reg_t bmsr;
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dscsr_reg_t dscsr;
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anlpar_reg_t anlpar;
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// BMSR is a latch low register
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// after power up, the first latched value must be 0, which means down
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// to speed up power up link speed, double read this register as a workaround
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
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eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
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/* check if link status changed */
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if (dm9051->phy_802_3.link_status != link) {
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/* when link up, read negotiation result */
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if (link == ETH_LINK_UP) {
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_DSCSR_REG_ADDR, &(dscsr.val)), err, TAG, "read DSCSR failed");
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if (dscsr.fdx100 || dscsr.hdx100) {
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speed = ETH_SPEED_100M;
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} else {
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speed = ETH_SPEED_10M;
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}
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if (dscsr.fdx100 || dscsr.fdx10) {
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duplex = ETH_DUPLEX_FULL;
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} else {
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duplex = ETH_DUPLEX_HALF;
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}
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
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/* if we're in duplex mode, and peer has the flow control ability */
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if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
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peer_pause_ability = 1;
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} else {
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peer_pause_ability = 0;
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}
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
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}
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ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
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dm9051->phy_802_3.link_status = link;
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}
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t dm9051_get_link(esp_eth_phy_t *phy)
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{
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esp_err_t ret = ESP_OK;
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phy_dm9051_t *dm9051 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_dm9051_t, phy_802_3);
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/* Update information about link, speed, duplex */
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ESP_GOTO_ON_ERROR(dm9051_update_link_duplex_speed(dm9051), err, TAG, "update link duplex speed failed");
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t dm9051_reset(esp_eth_phy_t *phy)
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{
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esp_err_t ret = ESP_OK;
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phy_dm9051_t *dm9051 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_dm9051_t, phy_802_3);
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uint32_t addr = dm9051->phy_802_3.addr;
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dm9051->phy_802_3.link_status = ETH_LINK_DOWN;
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esp_eth_mediator_t *eth = dm9051->phy_802_3.eth;
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dscr_reg_t dscr;
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_DSCR_REG_ADDR, &(dscr.val)), err, TAG, "read DSCR failed");
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dscr.smrst = 1;
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ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, addr, ETH_PHY_DSCR_REG_ADDR, dscr.val), err, TAG, "write DSCR failed");
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bmcr_reg_t bmcr = {.reset = 1};
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ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
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/* Wait for reset complete */
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uint32_t to = 0;
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for (to = 0; to < dm9051->phy_802_3.reset_timeout_ms / 10; to++) {
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vTaskDelay(pdMS_TO_TICKS(10));
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
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ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_DSCR_REG_ADDR, &(dscr.val)), err, TAG, "read DSCR failed");
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if (!bmcr.reset && !dscr.smrst) {
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break;
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}
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}
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ESP_GOTO_ON_FALSE(to < dm9051->phy_802_3.reset_timeout_ms / 10, ESP_FAIL, err, TAG, "PHY reset timeout");
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t dm9051_init(esp_eth_phy_t *phy)
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{
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esp_err_t ret = ESP_OK;
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phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
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/* Basic PHY init */
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ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
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/* Check PHY ID */
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uint32_t oui;
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uint8_t model;
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ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
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ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
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ESP_GOTO_ON_FALSE(oui == 0x606E && model == 0x0A, ESP_FAIL, err, TAG, "wrong chip ID");
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return ESP_OK;
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err:
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return ret;
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}
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esp_eth_phy_t *esp_eth_phy_new_dm9051(const eth_phy_config_t *config)
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{
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esp_eth_phy_t *ret = NULL;
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phy_dm9051_t *dm9051 = calloc(1, sizeof(phy_dm9051_t));
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ESP_GOTO_ON_FALSE(dm9051, NULL, err, TAG, "calloc dm9051 failed");
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ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&dm9051->phy_802_3, config) == ESP_OK,
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NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
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// redefine functions which need to be customized for sake of dm9051
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dm9051->phy_802_3.parent.init = dm9051_init;
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dm9051->phy_802_3.parent.reset = dm9051_reset;
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dm9051->phy_802_3.parent.get_link = dm9051_get_link;
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return &dm9051->phy_802_3.parent;
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err:
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if (dm9051 != NULL) {
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free(dm9051);
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}
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return ret;
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}
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