esp-idf/components/soc
Jiang Jiang Jian c672fc54fd Merge branch 'feature/ledc_more_meaningful_parameter_names' into 'master'
Provided more meaningful parameter names by renaming 'bit_num' to 'duty_resoluti…

See merge request !1440
2017-12-01 19:33:53 +08:00
..
esp32 Merge branch 'feature/ledc_more_meaningful_parameter_names' into 'master' 2017-12-01 19:33:53 +08:00
include/soc Add logic to make external RAM usable with malloc() 2017-09-28 17:17:50 +08:00
test soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
component.mk Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00