Marius Vikhammer 57442c38bd core: fix cases where riscv SP were not 16 byte aligned ... RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.		2021-06-02 16:02:10 +08:00
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include/freertos	Merge branch 'bugfix/silent_asserts_v4.3' into 'release/v4.3'	2021-04-13 04:30:09 +00:00
port.c	freertos: Fix delay between interrupt request and trigger on RISC-V	2021-03-10 12:14:21 +08:00
portasm.S	core: fix cases where riscv SP were not 16 byte aligned	2021-06-02 16:02:10 +08:00