mirror of
https://github.com/espressif/esp-idf.git
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333553caf2
fix(hal/include): fix header violations in hal component fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h` fix(hal/include): Add comment for a far away `#endif` fix(hal/include): change scope for cpp guard ci: Remove components/hal/ comment from public headers check exceptions Add missing include macro sdkconfig.h for header files Add missing include macro stdbool.h for header files Add missing include macro stdint.h for header files Add missing capability guard macro for header files Add missing cpp guard macro for header files Remove some useless include macros Add some missing `inline` attribute for functions defined in header files Remove components/hal/ from public headers check exceptions fix(hal/include): fix invalid licenses fix(hal/include): fix invalid licenses fix(hal/include): add missing soc_caps.h fix(hal): include soc_caps.h before cap macro is used fix(hal): Remove unnecessary target check fix(hal): fix header and macro problems Add missing include macro Remove loop dependency in hal Add comment for far-away endif fix(hal): Add missing soc_caps.h ci: update check_copyright_ignore.txt Change the sequence of `#include` macro, cpp guard macro Change the wrap scope of capacity macro fix(hal): Change position of C++ guard to pass test
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for RTC CNTL (common part)
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#include "soc/soc_caps.h"
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#include "soc/lldesc.h"
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#include "hal/dma_types.h"
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#include "hal/rtc_hal.h"
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#include "hal/assert.h"
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#include "esp_attr.h"
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#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
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typedef struct rtc_cntl_link_buf_conf {
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uint32_t cfg[4]; /* 4 word for dma link buffer configuration */
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} rtc_cntl_link_buf_conf_t;
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void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
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{
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HAL_ASSERT(elem != NULL);
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HAL_ASSERT(buff != NULL);
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HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
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lldesc_t *plink = (lldesc_t *)elem;
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plink->eof = next ? 0 : 1;
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plink->owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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plink->size = size >> 4; /* in unit of 16 bytes */
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plink->length = size >> 4;
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plink->buf = buff;
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plink->offset = 0;
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plink->sosf = 0;
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STAILQ_NEXT(plink, qe) = next;
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return (void *)plink;
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}
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#if SOC_PM_SUPPORT_CPU_PD
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void rtc_cntl_hal_enable_cpu_retention(void *addr)
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{
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rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
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if (addr) {
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if (retent->cpu_pd_mem) {
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lldesc_t *plink = (lldesc_t *)retent->cpu_pd_mem;
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/* dma link buffer configure */
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rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf;
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pbuf->cfg[0] = 0;
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pbuf->cfg[1] = 0;
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pbuf->cfg[2] = 0;
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pbuf->cfg[3] = (uint32_t)-1;
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rtc_cntl_ll_set_cpu_retention_link_addr((uint32_t)plink);
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rtc_cntl_ll_enable_cpu_retention_clock();
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rtc_cntl_ll_enable_cpu_retention();
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}
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}
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}
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void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
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{
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rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
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if (addr) {
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if (retent->cpu_pd_mem) {
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rtc_cntl_ll_disable_cpu_retention();
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}
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}
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}
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#endif // SOC_PM_SUPPORT_CPU_PD
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