mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
874a720286
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
216 lines
9.6 KiB
C
216 lines
9.6 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/* ---------------------------- Register Layout ------------------------------ */
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/* The TWAI peripheral's registers are 8bits, however the ESP32-C3 can only access
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* peripheral registers every 32bits. Therefore each TWAI register is mapped to
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* the least significant byte of every 32bits.
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*/
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typedef volatile struct twai_dev_s {
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//Configuration and Control Registers
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union {
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struct {
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uint32_t rm: 1; /* MOD.0 Reset Mode */
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uint32_t lom: 1; /* MOD.1 Listen Only Mode */
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uint32_t stm: 1; /* MOD.2 Self Test Mode */
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uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
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uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
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};
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uint32_t val;
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} mode_reg; /* Address 0x0000 */
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union {
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struct {
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uint32_t tr: 1; /* CMR.0 Transmission Request */
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uint32_t at: 1; /* CMR.1 Abort Transmission */
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uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
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uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
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uint32_t srr: 1; /* CMR.4 Self Reception Request */
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uint32_t reserved5: 27; /* Internal Reserved */
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};
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uint32_t val;
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} command_reg; /* Address 0x0004 */
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union {
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struct {
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uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
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uint32_t dos: 1; /* SR.1 Data Overrun Status */
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uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */
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uint32_t tcs: 1; /* SR.3 Transmission Complete Status */
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uint32_t rs: 1; /* SR.4 Receive Status */
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uint32_t ts: 1; /* SR.5 Transmit Status */
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uint32_t es: 1; /* SR.6 Error Status */
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uint32_t bs: 1; /* SR.7 Bus Status */
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uint32_t ms: 1; /* SR.8 Miss Status */
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uint32_t reserved9: 23; /* Internal Reserved */
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};
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uint32_t val;
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} status_reg; /* Address 0x0008 */
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union {
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struct {
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uint32_t ri: 1; /* IR.0 Receive Interrupt */
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uint32_t ti: 1; /* IR.1 Transmit Interrupt */
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uint32_t ei: 1; /* IR.2 Error Interrupt */
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uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
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uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
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uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
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uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
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uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} interrupt_reg; /* Address 0x000C */
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union {
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struct {
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uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
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uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
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uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
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uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
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uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
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uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
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uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
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uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} interrupt_enable_reg; /* Address 0x0010 */
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uint32_t reserved_14;
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union {
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struct {
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uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
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uint32_t reserved13: 1; /* Internal Reserved */
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uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
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uint32_t reserved16: 16; /* Internal Reserved */
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};
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uint32_t val;
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} bus_timing_0_reg; /* Address 0x0018 */
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union {
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struct {
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uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
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uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
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uint32_t sam: 1; /* BTR1.7 Sampling*/
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} bus_timing_1_reg; /* Address 0x001C */
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uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
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uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
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uint32_t reserved_28; /* Address 0x0028 */
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//Capture and Counter Registers
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union {
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struct {
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uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
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uint32_t reserved5: 27; /* Internal Reserved */
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};
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uint32_t val;
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} arbitration_lost_captue_reg; /* Address 0x002C */
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union {
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struct {
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uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
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uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
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uint32_t errc: 2; /* ECC[7:6] Error Code */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} error_code_capture_reg; /* Address 0x0030 */
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union {
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struct {
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uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} error_warning_limit_reg; /* Address 0x0034 */
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union {
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struct {
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uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} rx_error_counter_reg; /* Address 0x0038 */
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union {
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struct {
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uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} tx_error_counter_reg; /* Address 0x003C */
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//Shared Registers (TX Buff/RX Buff/Acc Filter)
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union {
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struct {
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union {
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struct {
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uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} acr[4];
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union {
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struct {
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uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
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uint32_t reserved8: 24; /* Internal Reserved */
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};
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uint32_t val;
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} amr[4];
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uint32_t reserved_60;
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uint32_t reserved_64;
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uint32_t reserved_68;
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uint32_t reserved_6c;
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uint32_t reserved_70;
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} acceptance_filter;
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union {
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struct {
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uint32_t byte: 8; /* TX/RX Byte X [7:0] */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} tx_rx_buffer[13];
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}; /* Address 0x0040 - 0x0070 */
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//Misc Registers
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union {
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struct {
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uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
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uint32_t reserved7: 25; /* Internal Reserved */
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};
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uint32_t val;
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} rx_message_counter_reg; /* Address 0x0074 */
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uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
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union {
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struct {
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uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
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uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
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uint32_t reserved9: 23; /* Internal Reserved */
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};
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uint32_t val;
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} clock_divider_reg; /* Address 0x007C */
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} twai_dev_t;
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_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
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extern twai_dev_t TWAI;
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#ifdef __cplusplus
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}
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#endif
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