mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
e9badf51c7
1. Fix incorrect meaning of SDMMC.clock bits, synchronize the names with the TRM. 2. Choose input and output phases to satisfy typical timing requirements. 3. Move use_hold_reg setting into the host driver, since it is related to timing. Closes https://github.com/espressif/esp-idf/issues/8521 Related to https://github.com/espressif/esp-idf/issues/8257
398 lines
17 KiB
C
398 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct sdmmc_desc_s {
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struct {
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uint32_t reserved1: 1;
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uint32_t disable_int_on_completion: 1;
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uint32_t last_descriptor: 1;
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uint32_t first_descriptor: 1;
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uint32_t second_address_chained: 1;
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uint32_t end_of_ring: 1;
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uint32_t reserved2: 24;
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uint32_t card_error_summary: 1;
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uint32_t owned_by_idmac: 1;
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};
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struct {
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uint32_t buffer1_size: 13;
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uint32_t buffer2_size: 13;
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uint32_t reserved3: 6;
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};
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void* buffer1_ptr;
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union {
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void* buffer2_ptr;
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void* next_desc_ptr;
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};
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} sdmmc_desc_t;
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#define SDMMC_DMA_MAX_BUF_LEN 4096
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#ifndef __cplusplus
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_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
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#endif
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typedef struct sdmmc_hw_cmd_s {
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uint32_t cmd_index: 6; ///< Command index
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uint32_t response_expect: 1; ///< set if response is expected
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uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
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uint32_t check_response_crc: 1; ///< set if controller should check response CRC
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uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected
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uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected)
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uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
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uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer
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uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete
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uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer
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uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1)
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uint32_t card_num: 5; ///< card number
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uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers
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uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device
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uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device
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uint32_t enable_boot: 1; ///< set for mandatory boot mode
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uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern
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uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot)
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uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation
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uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only)
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uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register
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uint32_t reserved: 1;
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uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared.
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} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
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#ifndef __cplusplus
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_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
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#endif
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typedef volatile struct sdmmc_dev_s {
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union {
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struct {
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uint32_t controller_reset: 1;
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uint32_t fifo_reset: 1;
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uint32_t dma_reset: 1;
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uint32_t reserved1: 1;
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uint32_t int_enable: 1;
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uint32_t dma_enable: 1;
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uint32_t read_wait: 1;
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uint32_t send_irq_response: 1;
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uint32_t abort_read_data: 1;
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uint32_t send_ccsd: 1;
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uint32_t send_auto_stop_ccsd: 1;
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uint32_t ceata_device_interrupt_status: 1;
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uint32_t reserved2: 4;
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uint32_t card_voltage_a: 4;
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uint32_t card_voltage_b: 4;
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uint32_t enable_od_pullup: 1;
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uint32_t use_internal_dma: 1;
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uint32_t reserved3: 6;
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};
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uint32_t val;
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} ctrl;
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uint32_t pwren; ///< 1: enable power to card, 0: disable power to card
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union {
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struct {
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uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
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};
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uint32_t val;
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} clkdiv;
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union {
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struct {
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uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3
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uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3
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uint32_t reserved: 28;
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};
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uint32_t val;
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} clksrc;
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union {
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struct {
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uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock
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uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating
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};
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uint32_t val;
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} clkena;
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union {
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struct {
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uint32_t response: 8; ///< response timeout, in card output clock cycles
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uint32_t data: 24; ///< data read timeout, in card output clock cycles
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};
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uint32_t val;
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} tmout;
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union {
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struct {
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uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
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uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
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};
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uint32_t val;
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} ctype;
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struct {
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uint32_t blksiz: 16; ///< block size, default 0x200
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uint32_t reserved: 16;
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};
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uint32_t bytcnt; ///< number of bytes to be transferred
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union {
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struct {
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uint32_t cd: 1; ///< Card detect interrupt enable
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uint32_t re: 1; ///< Response error interrupt enable
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uint32_t cmd_done: 1; ///< Command done interrupt enable
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uint32_t dto: 1; ///< Data transfer over interrupt enable
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uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable
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uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable
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uint32_t rcrc: 1; ///< Response CRC error interrupt enable
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uint32_t dcrc: 1; ///< Data CRC error interrupt enable
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uint32_t rto: 1; ///< Response timeout interrupt enable
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uint32_t drto: 1; ///< Data read timeout interrupt enable
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uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable
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uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable
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uint32_t hle: 1; ///< Hardware locked write error interrupt enable
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uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable
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uint32_t acd: 1; ///< Auto command done interrupt enable
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uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable
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uint32_t sdio: 16; ///< SDIO interrupt enable
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};
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uint32_t val;
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} intmask;
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uint32_t cmdarg; ///< Command argument to be passed to card
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sdmmc_hw_cmd_t cmd;
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uint32_t resp[4]; ///< Response from card
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union {
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struct {
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uint32_t cd: 1; ///< Card detect interrupt masked status
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uint32_t re: 1; ///< Response error interrupt masked status
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uint32_t cmd_done: 1; ///< Command done interrupt masked status
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uint32_t dto: 1; ///< Data transfer over interrupt masked status
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uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status
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uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status
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uint32_t rcrc: 1; ///< Response CRC error interrupt masked status
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uint32_t dcrc: 1; ///< Data CRC error interrupt masked status
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uint32_t rto: 1; ///< Response timeout interrupt masked status
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uint32_t drto: 1; ///< Data read timeout interrupt masked status
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uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status
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uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status
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uint32_t hle: 1; ///< Hardware locked write error interrupt masked status
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uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status
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uint32_t acd: 1; ///< Auto command done interrupt masked status
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uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status
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uint32_t sdio: 16; ///< SDIO interrupt masked status
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};
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uint32_t val;
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} mintsts;
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union {
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struct {
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uint32_t cd: 1; ///< Card detect raw interrupt status
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uint32_t re: 1; ///< Response error raw interrupt status
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uint32_t cmd_done: 1; ///< Command done raw interrupt status
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uint32_t dto: 1; ///< Data transfer over raw interrupt status
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uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status
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uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status
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uint32_t rcrc: 1; ///< Response CRC error raw interrupt status
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uint32_t dcrc: 1; ///< Data CRC error raw interrupt status
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uint32_t rto: 1; ///< Response timeout raw interrupt status
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uint32_t drto: 1; ///< Data read timeout raw interrupt status
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uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status
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uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status
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uint32_t hle: 1; ///< Hardware locked write error raw interrupt status
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uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status
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uint32_t acd: 1; ///< Auto command done raw interrupt status
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uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status
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uint32_t sdio: 16; ///< SDIO raw interrupt status
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};
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uint32_t val;
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} rintsts; ///< interrupts can be cleared by writing this register
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union {
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struct {
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uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level
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uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level
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uint32_t fifo_empty: 1; ///< FIFO is empty
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uint32_t fifo_full: 1; ///< FIFO is full
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uint32_t cmd_fsm_state: 4; ///< command FSM state
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uint32_t data3_status: 1; ///< this bit reads 1 if card is present
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uint32_t data_busy: 1; ///< this bit reads 1 if card is busy
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uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy
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uint32_t response_index: 6; ///< index of the previous response
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uint32_t fifo_count: 13; ///< number of filled locations in the FIFO
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uint32_t dma_ack: 1; ///< DMA acknowledge signal
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uint32_t dma_req: 1; ///< DMA request signal
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};
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uint32_t val;
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} status;
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union {
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struct {
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uint32_t tx_watermark: 12; ///< FIFO TX watermark level
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uint32_t reserved1: 4;
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uint32_t rx_watermark: 12; ///< FIFO RX watermark level
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uint32_t dw_dma_mts: 3;
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uint32_t reserved2: 1;
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};
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uint32_t val;
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} fifoth;
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union {
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struct {
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uint32_t cards: 2; ///< bit N reads 0 if card N is present
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uint32_t reserved: 30;
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};
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uint32_t val;
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} cdetect;
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union {
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struct {
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uint32_t cards: 2; ///< bit N reads 1 if card N is write protected
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uint32_t reserved: 30;
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};
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uint32_t val;
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} wrtprt;
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uint32_t gpio; ///< unused
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uint32_t tcbcnt; ///< transferred (to card) byte count
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uint32_t tbbcnt; ///< transferred from host to FIFO byte count
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union {
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struct {
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uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms
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uint32_t reserved: 8;
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};
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} debnce;
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uint32_t usrid; ///< user ID
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uint32_t verid; ///< IP block version
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uint32_t hcon; ///< compile-time IP configuration
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union {
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struct {
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uint32_t voltage: 16; ///< voltage control for slots; no-op on ESP32.
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uint32_t ddr: 16; ///< bit N enables DDR mode for card N
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};
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} uhs; ///< UHS related settings
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union {
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struct {
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uint32_t cards: 2; ///< bit N resets card N, active low
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uint32_t reserved: 30;
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};
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} rst_n;
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uint32_t reserved_7c;
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union {
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struct {
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uint32_t sw_reset: 1; ///< set to reset DMA controller
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uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers
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uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors
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uint32_t enable: 1; ///< set to enable IDMAC
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uint32_t pbl: 3; ///< programmable burst length
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uint32_t reserved: 21;
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};
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uint32_t val;
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} bmod;
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uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
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sdmmc_desc_t* dbaddr; ///< descriptor list base
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union {
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struct {
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uint32_t ti: 1; ///< transmit interrupt status
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uint32_t ri: 1; ///< receive interrupt status
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uint32_t fbe: 1; ///< fatal bus error
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uint32_t reserved1: 1;
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uint32_t du: 1; ///< descriptor unavailable
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uint32_t ces: 1; ///< card error summary
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uint32_t reserved2: 2;
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uint32_t nis: 1; ///< normal interrupt summary
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uint32_t ais: 1; ///< abnormal interrupt summary
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uint32_t fbe_code: 3; ///< code of fatal bus error
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uint32_t fsm: 4; ///< DMAC FSM state
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uint32_t reserved3: 15;
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};
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uint32_t val;
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} idsts;
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union {
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struct {
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uint32_t ti: 1; ///< transmit interrupt enable
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uint32_t ri: 1; ///< receive interrupt enable
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uint32_t fbe: 1; ///< fatal bus error interrupt enable
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uint32_t reserved1: 1;
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uint32_t du: 1; ///< descriptor unavailable interrupt enable
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uint32_t ces: 1; ///< card error interrupt enable
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uint32_t reserved2: 2;
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uint32_t ni: 1; ///< normal interrupt interrupt enable
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uint32_t ai: 1; ///< abnormal interrupt enable
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uint32_t reserved3: 22;
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};
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uint32_t val;
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} idinten;
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uint32_t dscaddr; ///< current host descriptor address
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uint32_t dscaddrl; ///< unused
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uint32_t dscaddru; ///< unused
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uint32_t bufaddrl; ///< unused
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uint32_t bufaddru; ///< unused
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uint32_t reserved_a8[22];
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union {
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struct {
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uint32_t read_thr_en : 1; ///< initiate transfer only if FIFO has more space than the read threshold
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uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts
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uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
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uint32_t reserved1 : 13;
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uint32_t card_threshold : 16; ///< threshold value for reads/writes, in bytes
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};
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uint32_t val;
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} cardthrctl;
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uint32_t back_end_power;
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uint32_t uhs_reg_ext;
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uint32_t emmc_ddr_reg;
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uint32_t enable_shift;
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uint32_t reserved_114[443];
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union {
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struct {
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uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
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uint32_t phase_din: 3; ///< phase of data input clock
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uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
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uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
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uint32_t div_factor_l: 4; ///< controls clock period; it will be (div_factor_l + 1) / 160MHz
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uint32_t div_factor_n: 4; ///< should be equal to div_factor_l
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uint32_t reserved1 : 2;
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uint32_t clk_sel : 1; ///< clock source select (0: XTAL, 1: 160 MHz from PLL)
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} clock;
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} sdmmc_dev_t;
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extern sdmmc_dev_t SDMMC;
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#ifndef __cplusplus
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_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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