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485 lines
18 KiB
C
485 lines
18 KiB
C
/* MEMPROT IramDram testing code */
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#include <stdio.h>
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#include "sdkconfig.h"
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#include "esp_spi_flash.h"
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#include "esp32s2/memprot.h"
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#include <string.h>
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#include "esp_log.h"
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/*
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* ESP32S2 MEMORY PROTECTION MODULE TEST
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* =====================================
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*
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* In order to safely test all the mem_prot features, this test uses a proprietary setting
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* for all splitting addresses, ie it partially overrides production settings.
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* Each operation is tested at [test-splitting-addr - 16B] (low region) and
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* [test-splitting-addr + 16B] (high region). Complete testing scheme
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* is depicted below, the addresses used come from this application binary:
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*
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* ********************************************************************************************
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*
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* IRAM0 SRAM (320kB) DRAM0
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* ===========================
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* (_iram_text_end) | | (_data_start)
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* 0x4002B51C(!) <-------- real splt.addr --------> 0x3FFBB520
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* | |
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* 0x4002DA30 <---|-------------------------|--> 0x3FFBDA30
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* | test buffer (64 kB) |
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* | ... |
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* 0x40035A30 <-------- test splt.addr --------> 0x3FFC5A30
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* | ... |
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* |-------------------------|
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* | |
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* ===========================
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*
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* RTC_FAST (8kB)
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* (_rtc_text_end) =========================== (_rtc_dummy_end)
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* 0x40070000 <-------- real splt.addr --------> 0x3FF9E000
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* | |
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* | test buffer (7 kB) |
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* | ... |
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* 0x40070E00 <-------- test splt.addr --------> 0x3FF9EE00
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* | ... |
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* |-------------------------|
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* | |
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* ===========================
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*
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* ********************************************************************************************
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*
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* PERIBUS_1 RTC_SLOW (8/768kB) PERIBUS_2_0 PERIBUS_2_1
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* ===========================
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* | |
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* 0x3F421000 <-------- real splt.addr --------> 0x50000000 0x60021000
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* | |
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* | test buffer (7 kB) |
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* | ... |
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* 0x3F421E00 <-------- test splt.addr --------> 0x50000E00 0x60021E00
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* | ... |
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* |-------------------------|
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* | |
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* ===========================
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*
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* ********************************************************************************************
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*/
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/* !!!IMPORTANT!!!
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* a0 needs to be saved/restored manually (not clobbered) to avoid return address corruption
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* caused by ASM block handling
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*/
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#define CODE_EXEC(code_buf, param, res) \
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asm volatile ( \
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"mov a3, a0\n\t" \
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"movi a2," #param "\n\t" \
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"callx0 %1\n\t" \
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"mov %0,a2\n\t" \
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"mov a0, a3\n\t" \
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: "=r"(res) \
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: "r"(code_buf) \
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: "a2", "a3" );
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/* Binary code for the following asm:
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*
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.type _testfunc,@function
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.global _testfunc
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.align 4
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_testfunc:
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slli a2, a2, 1
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ret.n
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*/
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static uint8_t fnc_call0_buff[] = {0xf0, 0x22, 0x11, 0x0d, 0xf0, 0x00, 0x00, 0x00};
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#define SRAM_DUMMY_BUFFER_SIZE 64*1024
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#define RTCFAST_DUMMY_BUFFER_SIZE 7*1024
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#define RTCSLOW_DUMMY_BUFFER_SIZE 7*1024
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volatile bool g_override_illegal_instruction = false;
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static uint8_t sram_dummy_buffer[SRAM_DUMMY_BUFFER_SIZE] = {0};
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static uint8_t RTC_FAST_ATTR rtcfast_dummy_buffer[RTCFAST_DUMMY_BUFFER_SIZE] = {0};
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static uint8_t RTC_SLOW_ATTR rtcslow_dummy_buffer[RTCSLOW_DUMMY_BUFFER_SIZE] = {0};
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/* ********************************************************************************************
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* testing regions and splitting address scheme
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*
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*/
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static uint32_t *test_memprot_dram0_sram_get_min_split_addr(void)
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{
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return (uint32_t *)(sram_dummy_buffer + sizeof(sram_dummy_buffer) / 2);
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}
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static uint32_t *test_memprot_dram0_rtcfast_get_min_split_addr(void)
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{
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return (uint32_t *)(rtcfast_dummy_buffer + sizeof(rtcfast_dummy_buffer) / 2);
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}
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static uint32_t *test_memprot_iram0_sram_get_min_split_addr(void)
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{
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return (uint32_t *)
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((uint32_t)test_memprot_dram0_sram_get_min_split_addr() +
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+ esp_memprot_get_low_limit(MEMPROT_IRAM0_SRAM)
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- esp_memprot_get_low_limit(MEMPROT_DRAM0_SRAM));
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}
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static uint32_t *test_memprot_iram0_rtcfast_get_min_split_addr(void)
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{
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return (uint32_t *)
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((uint32_t)test_memprot_dram0_rtcfast_get_min_split_addr()
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+ esp_memprot_get_low_limit(MEMPROT_IRAM0_RTCFAST)
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- esp_memprot_get_low_limit(MEMPROT_DRAM0_RTCFAST));
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}
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static uint32_t *test_memprot_peri2_rtcslow_0_get_min_split_addr(void)
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{
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return (uint32_t *)(rtcslow_dummy_buffer + sizeof(rtcslow_dummy_buffer) / 2);
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}
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static uint32_t *test_memprot_peri1_rtcslow_get_min_split_addr(void)
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{
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return (uint32_t *)
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((uint32_t)test_memprot_peri2_rtcslow_0_get_min_split_addr()
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- (esp_memprot_get_low_limit(MEMPROT_PERI2_RTCSLOW_0)
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- esp_memprot_get_low_limit(MEMPROT_PERI1_RTCSLOW)));
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}
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static uint32_t *test_memprot_peri2_rtcslow_1_get_min_split_addr(void)
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{
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return (uint32_t *)
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((uint32_t)test_memprot_peri2_rtcslow_0_get_min_split_addr()
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+ esp_memprot_get_low_limit(MEMPROT_PERI2_RTCSLOW_1)
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- esp_memprot_get_low_limit(MEMPROT_PERI2_RTCSLOW_0));
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}
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static uint32_t *test_memprot_get_split_addr(mem_type_prot_t mem_type)
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{
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switch (mem_type) {
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case MEMPROT_IRAM0_SRAM:
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return test_memprot_iram0_sram_get_min_split_addr();
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case MEMPROT_DRAM0_SRAM:
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return test_memprot_dram0_sram_get_min_split_addr();
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case MEMPROT_IRAM0_RTCFAST:
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return test_memprot_iram0_rtcfast_get_min_split_addr();
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case MEMPROT_DRAM0_RTCFAST:
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return test_memprot_dram0_rtcfast_get_min_split_addr();
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case MEMPROT_PERI1_RTCSLOW:
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return test_memprot_peri1_rtcslow_get_min_split_addr();
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case MEMPROT_PERI2_RTCSLOW_0:
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return test_memprot_peri2_rtcslow_0_get_min_split_addr();
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case MEMPROT_PERI2_RTCSLOW_1:
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return test_memprot_peri2_rtcslow_1_get_min_split_addr();
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default:
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abort();
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}
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}
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/*
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* testing setup of the memory-protection module
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*/
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static void test_memprot_set_prot(uint32_t *mem_type_mask, bool use_panic_handler)
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{
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//any IRAM0/DRAM0 enable/disable call applies to all memory modules connected
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uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask;
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bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM || required_mem_prot & MEMPROT_IRAM0_RTCFAST;
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bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM || required_mem_prot & MEMPROT_DRAM0_RTCFAST;
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bool use_peri1 = required_mem_prot & MEMPROT_PERI1_RTCSLOW;
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bool use_peri2 = required_mem_prot & MEMPROT_PERI2_RTCSLOW_0 || required_mem_prot & MEMPROT_PERI2_RTCSLOW_1;
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//disable protection
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if (use_iram0) {
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esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, false);
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}
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if (use_dram0) {
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esp_memprot_intr_ena(MEMPROT_DRAM0_SRAM, false);
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}
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if (use_peri1) {
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esp_memprot_intr_ena(MEMPROT_PERI1_RTCSLOW, false);
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}
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if (use_peri2) {
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esp_memprot_intr_ena(MEMPROT_PERI2_RTCSLOW_0, false);
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}
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if ( use_panic_handler ) {
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if (use_iram0) {
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esp_memprot_intr_init(MEMPROT_IRAM0_SRAM);
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}
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if (use_dram0) {
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esp_memprot_intr_init(MEMPROT_DRAM0_SRAM);
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}
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if (use_peri1) {
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esp_memprot_intr_init(MEMPROT_PERI1_RTCSLOW);
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}
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if (use_peri2) {
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esp_memprot_intr_init(MEMPROT_PERI2_RTCSLOW_0);
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}
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}
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//set permissions
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if (required_mem_prot & MEMPROT_IRAM0_SRAM) {
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esp_memprot_set_prot_iram(MEMPROT_IRAM0_SRAM, test_memprot_iram0_sram_get_min_split_addr(), true, true, true, true, true, false);
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}
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if (required_mem_prot & MEMPROT_IRAM0_RTCFAST) {
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esp_memprot_set_prot_iram(MEMPROT_IRAM0_RTCFAST, test_memprot_iram0_rtcfast_get_min_split_addr(), false, true, true, true, true, false);
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}
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if (required_mem_prot & MEMPROT_DRAM0_SRAM) {
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esp_memprot_set_prot_dram(MEMPROT_DRAM0_SRAM, test_memprot_dram0_sram_get_min_split_addr(), true, true, true, true);
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}
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if (required_mem_prot & MEMPROT_DRAM0_RTCFAST) {
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esp_memprot_set_prot_dram(MEMPROT_DRAM0_RTCFAST, test_memprot_dram0_rtcfast_get_min_split_addr(), false, true, true, true);
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}
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if (required_mem_prot & MEMPROT_PERI1_RTCSLOW) {
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esp_memprot_set_prot_peri1(MEMPROT_PERI1_RTCSLOW, test_memprot_peri1_rtcslow_get_min_split_addr(), true, true, true, true);
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}
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if (required_mem_prot & MEMPROT_PERI2_RTCSLOW_0) {
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esp_memprot_set_prot_peri2(MEMPROT_PERI2_RTCSLOW_0, test_memprot_peri2_rtcslow_0_get_min_split_addr(), true, true, false, true, true, false);
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}
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if (required_mem_prot & MEMPROT_PERI2_RTCSLOW_1) {
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esp_memprot_set_prot_peri2(MEMPROT_PERI2_RTCSLOW_1, test_memprot_peri2_rtcslow_1_get_min_split_addr(), true, true, false, true, true, false);
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}
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//reenable protection (bus based)
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if (use_iram0) {
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esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, true);
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}
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if (use_dram0) {
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esp_memprot_intr_ena(MEMPROT_DRAM0_SRAM, true);
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}
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if (use_peri1) {
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esp_memprot_intr_ena(MEMPROT_PERI1_RTCSLOW, true);
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}
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if (use_peri2) {
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esp_memprot_intr_ena(MEMPROT_PERI2_RTCSLOW_0, true);
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}
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}
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/* ********************************************************************************************
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* auxiliary functions
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*/
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static void __attribute__((unused)) dump_fnc_buff(uint32_t *buff)
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{
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esp_rom_printf( "0x%08X: 0x%08X-0x%08X\n", (uint32_t)buff, buff[0], buff[1] );
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}
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static void __attribute__((unused)) dump_bus_permissions(mem_type_prot_t mem_type)
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{
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bool write_perm_low, write_perm_high, read_perm_low, read_perm_high, exec_perm_low, exec_perm_high;
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esp_memprot_get_permissions(mem_type, &write_perm_low, &write_perm_high, &read_perm_low, &read_perm_high, &exec_perm_low, &exec_perm_high);
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esp_rom_printf("%s permissions: LW=%u LR=%u LX=%u HW=%u HR=%u HX=%u\n", esp_memprot_type_to_str(mem_type),
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write_perm_low, read_perm_low, exec_perm_low, write_perm_high, read_perm_high, exec_perm_high);
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}
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static void __attribute__((unused)) dump_status_register(mem_type_prot_t mem_type)
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{
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uint32_t *faulting_address, op_type, op_subtype;
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esp_memprot_get_fault_status(mem_type, &faulting_address, &op_type, &op_subtype);
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esp_rom_printf(
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" FAULT [split addr: 0x%08X, fault addr: 0x%08X, fault status: 0x%08X]\n",
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(uint32_t)test_memprot_get_split_addr(mem_type),
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(uint32_t)faulting_address,
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esp_memprot_get_fault_reg(mem_type)
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);
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}
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/* ********************************************************************************************
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* testing functions
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*/
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static void check_test_result(mem_type_prot_t mem_type, bool expected_status)
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{
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uint32_t fault = esp_memprot_get_fault_reg(mem_type);
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bool test_result = expected_status ? fault == 0 : fault != 0;
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if ( test_result ) {
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esp_rom_printf("OK\n");
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} else {
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dump_status_register(mem_type);
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}
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}
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static void test_memprot_read(mem_type_prot_t mem_type)
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{
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//get current READ & WRITE permission settings
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bool write_perm_low, write_perm_high, read_perm_low, read_perm_high;
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esp_memprot_get_perm_read(mem_type, &write_perm_low, &write_perm_high);
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esp_memprot_get_perm_read(mem_type, &read_perm_low, &read_perm_high);
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//get current splitting address
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volatile uint32_t *ptr = test_memprot_get_split_addr(mem_type);
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//temporarily allow WRITE for setting the test values
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const uint32_t test_val = 100;
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esp_memprot_set_write_perm(mem_type, true, true);
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*(ptr - 4) = test_val;
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*(ptr + 4) = test_val + 1;
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esp_memprot_set_write_perm(mem_type, write_perm_low, write_perm_high);
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//perform READ in low region
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esp_rom_printf("%s read low: ", esp_memprot_type_to_str(mem_type));
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esp_memprot_clear_intr(mem_type);
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volatile uint32_t val = *(ptr - 4);
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if ( val != 0 && val != test_val ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val );
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, val == test_val);
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}
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//perform read in high region
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esp_rom_printf("%s read high: ", esp_memprot_type_to_str(mem_type));
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esp_memprot_clear_intr(mem_type);
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val = *(ptr + 4);
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if ( val != 0 && val != (test_val + 1) ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val);
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, val == (test_val + 1));
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}
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}
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static void test_memprot_write(mem_type_prot_t mem_type)
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{
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//get current READ & WRITE permission settings
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bool write_perm_low, write_perm_high, read_perm_low, read_perm_high;
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esp_memprot_get_perm_read(mem_type, &write_perm_low, &write_perm_high);
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esp_memprot_get_perm_read(mem_type, &read_perm_low, &read_perm_high);
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//temporarily allow READ operation
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esp_memprot_set_read_perm(mem_type, true, true);
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//get current splitting address
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volatile uint32_t *ptr = test_memprot_get_split_addr(mem_type);
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//perform WRITE in low region
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const uint32_t test_val = 10;
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esp_rom_printf("%s write low: ", esp_memprot_type_to_str(mem_type));
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esp_memprot_clear_intr(mem_type);
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volatile uint32_t val = 0;
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*(ptr - 4) = test_val;
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val = *(ptr - 4);
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if ( val != test_val && write_perm_low ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val);
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, write_perm_low);
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}
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//perform WRITE in high region
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esp_rom_printf("%s write high: ", esp_memprot_type_to_str(mem_type));
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esp_memprot_clear_intr(mem_type);
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val = 0;
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*(ptr + 4) = test_val + 1;
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val = *(ptr + 4);
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if ( val != (test_val + 1) && write_perm_high ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val);
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, write_perm_high);
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}
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}
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static void test_memprot_exec(mem_type_prot_t mem_type)
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{
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//store current write permissions
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bool write_perm_low, write_perm_high;
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esp_memprot_get_perm_write(mem_type, &write_perm_low, &write_perm_high);
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//get current EXEC permission settings
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bool exec_perm_low, exec_perm_high;
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esp_memprot_get_perm_exec(mem_type, &exec_perm_low, &exec_perm_high);
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volatile uint32_t *fnc_ptr_low = (uint32_t *)(test_memprot_get_split_addr(mem_type) - 4);
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volatile uint32_t *fnc_ptr_high = (uint32_t *)(test_memprot_get_split_addr(mem_type) + 4);
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//enable WRITE permission for both segments
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esp_memprot_set_write_perm(mem_type, true, true);
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//inject the code to both low & high segments
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memcpy( (void *)fnc_ptr_low, fnc_call0_buff, sizeof(fnc_call0_buff) );
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memcpy( (void *)fnc_ptr_high, fnc_call0_buff, sizeof(fnc_call0_buff) );
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//restore original WRITE perms
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esp_memprot_set_write_perm(mem_type, write_perm_low, write_perm_high);
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uint32_t res = 0;
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//LOW REGION: clear the intr flag & try to execute the code injected
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esp_memprot_clear_intr(mem_type);
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esp_rom_printf("%s exec low: ", esp_memprot_type_to_str(mem_type));
|
|
|
|
g_override_illegal_instruction = true;
|
|
CODE_EXEC(fnc_ptr_low, 5, res);
|
|
g_override_illegal_instruction = false;
|
|
|
|
//check results
|
|
bool fnc_call_ok = res == 10;
|
|
if ( fnc_call_ok ) {
|
|
check_test_result(mem_type, exec_perm_low);
|
|
} else {
|
|
if ( !exec_perm_low ) {
|
|
check_test_result(mem_type, true);
|
|
} else {
|
|
esp_rom_printf(" FAULT [injected code not executed]\n");
|
|
}
|
|
}
|
|
|
|
//HIGH REGION: clear the intr flag & try to execute the code injected
|
|
esp_memprot_clear_intr(mem_type);
|
|
esp_rom_printf("%s exec high: ", esp_memprot_type_to_str(mem_type));
|
|
|
|
g_override_illegal_instruction = true;
|
|
CODE_EXEC(fnc_ptr_high, 6, res);
|
|
g_override_illegal_instruction = false;
|
|
|
|
fnc_call_ok = res == 12;
|
|
if ( fnc_call_ok ) {
|
|
check_test_result(mem_type, exec_perm_high);
|
|
} else {
|
|
if ( !exec_perm_high ) {
|
|
check_test_result(mem_type, true);
|
|
} else {
|
|
esp_rom_printf(" FAULT [injected code not executed]\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* ********************************************************************************************
|
|
* main test runner
|
|
*/
|
|
void app_main(void)
|
|
{
|
|
test_memprot_set_prot(NULL, false);
|
|
|
|
test_memprot_read(MEMPROT_IRAM0_SRAM);
|
|
test_memprot_write(MEMPROT_IRAM0_SRAM);
|
|
test_memprot_exec(MEMPROT_IRAM0_SRAM);
|
|
|
|
test_memprot_read(MEMPROT_IRAM0_RTCFAST);
|
|
test_memprot_write(MEMPROT_IRAM0_RTCFAST);
|
|
test_memprot_exec(MEMPROT_IRAM0_RTCFAST);
|
|
|
|
test_memprot_read(MEMPROT_DRAM0_SRAM);
|
|
test_memprot_write(MEMPROT_DRAM0_SRAM);
|
|
|
|
test_memprot_read(MEMPROT_DRAM0_RTCFAST);
|
|
test_memprot_write(MEMPROT_DRAM0_RTCFAST);
|
|
|
|
test_memprot_read(MEMPROT_PERI1_RTCSLOW);
|
|
test_memprot_write(MEMPROT_PERI1_RTCSLOW);
|
|
|
|
test_memprot_read(MEMPROT_PERI2_RTCSLOW_0);
|
|
test_memprot_write(MEMPROT_PERI2_RTCSLOW_0);
|
|
test_memprot_exec(MEMPROT_PERI2_RTCSLOW_0);
|
|
|
|
test_memprot_read(MEMPROT_PERI2_RTCSLOW_1);
|
|
test_memprot_write(MEMPROT_PERI2_RTCSLOW_1);
|
|
test_memprot_exec(MEMPROT_PERI2_RTCSLOW_1);
|
|
}
|