mirror of
https://github.com/espressif/esp-idf.git
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cb6e2133f0
The commit fixes the case: If variables in RTC RAM have been moved around by the linker, they will be filled with garbage data. Any reset other than OTA would work fine because the variables would still be initialized from the initial bootup. So now system time will be valid even after OTA. Closes https://github.com/espressif/esp-idf/issues/9448
176 lines
6.6 KiB
Plaintext
176 lines
6.6 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ESP32 Linker Script Memory Layout
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This file describes the memory layout (memory blocks) as virtual
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memory addresses.
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esp32.project.ld contains output sections to link compiler output
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into these memory blocks.
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***
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This linker script is passed through the C preprocessor to include
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configuration options.
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Please use preprocessor features sparingly! Restrict
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to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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#include "ld.common"
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/* If BT is not built at all */
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#ifndef CONFIG_BTDM_RESERVE_DRAM
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#define CONFIG_BTDM_RESERVE_DRAM 0
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#endif
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#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
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ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200),
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"Fixed static ram data does not fit.")
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#define DRAM0_0_SEG_LEN CONFIG_ESP32_FIXED_STATIC_RAM_SIZE
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#else
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#define DRAM0_0_SEG_LEN 0x2c200
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#endif
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#if CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM
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#define SRAM1_IRAM_LEN 0xA000
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#else
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#define SRAM1_IRAM_LEN 0x0
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#endif
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 + SRAM1_IRAM_LEN
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Even though the segment name is iram, it is actually mapped to flash
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*/
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iram0_2_seg (RX) : org = 0x400D0020, len = 0x330000-0x20
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/*
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(0x20 offset above is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
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header. Setting this offset makes it simple to meet the flash cache MMU's
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constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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the amount of RAM available.
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Note: Length of this section *should* be 0x50000, and this extra DRAM is available
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in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
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additional static memory temporarily cannot be used.
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*/
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dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BTDM_RESERVE_DRAM,
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len = DRAM0_0_SEG_LEN - CONFIG_BTDM_RESERVE_DRAM
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* RTC fast memory (executable). Persists over deep sleep. */
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
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/* RTC fast memory (same block as above, rtc_iram_seg), viewed from data bus */
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rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
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/* We reduced the size of rtc_iram_seg and rtc_data_seg by ESP_BOOTLOADER_RESERVE_RTC value.
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It reserves the amount of RTC fast memory that we use for this memory segment.
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This segment is intended for keeping bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
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The aim of this is to keep data that will not be moved around and have a fixed address.
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org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC == SOC_RTC_DRAM_HIGH - sizeof(rtc_retain_mem_t)
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*/
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rtc_fast_reserved_seg(RW) : org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC, len = ESP_BOOTLOADER_RESERVE_RTC
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/* RTC slow memory (data accessible). Persists over deep sleep.
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Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
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*/
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#if CONFIG_ULP_COPROC_ENABLED
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
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len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
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#else
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rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000 - RESERVE_RTC_MEM
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#endif // CONFIG_ULP_COPROC_ENABLED
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/* We reduced the size of rtc_slow_seg by RESERVE_RTC_MEM value.
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It reserves the amount of RTC slow memory that we use for this memory segment.
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This segment is intended for keeping rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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The aim of this is to keep data that will not be moved around and have a fixed address.
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org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM
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*/
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rtc_slow_reserved_seg(RW) : org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
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/* external memory */
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extern_ram_seg(RWX) : org = 0x3F800000,
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len = 0x400000
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}
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#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
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/* static data ends at defined address */
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_heap_start = 0x3FFB0000 + DRAM0_0_SEG_LEN;
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#else
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_heap_start = _heap_low_start;
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#endif
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_sram1_iram_start = 0x400A0000;
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_sram1_iram_len = ( _iram_end > _sram1_iram_start) ? (_iram_end - _sram1_iram_start) : 0;
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_heap_end = ALIGN(0x40000000 - _sram1_iram_len - 3, 4);
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#if CONFIG_ESP32_TRACEMEM_RESERVE_DRAM != 0
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_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
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#endif
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_data_seg_org = ORIGIN(rtc_data_seg);
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/* The lines below define location alias for .rtc.data section based on Kconfig option.
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When the option is not defined then use slow memory segment
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else the data will be placed in fast memory segment */
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#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
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REGION_ALIAS("rtc_data_location", rtc_slow_seg );
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#else
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REGION_ALIAS("rtc_data_location", rtc_data_seg );
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#endif
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_code_seg", iram0_2_seg);
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#else
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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#else
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
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* also be first in the segment.
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*/
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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ASSERT(_rodata_start == ORIGIN(default_rodata_seg),
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".flash.appdesc section must be placed at the beginning of the rodata segment.")
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#endif
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