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e5b280f173
A new method of workaround an error with DPORT is to ensure that the APB is read and followed by the DPORT register without interruptions and pauses. This fix places this implementation in the IRAM to exclude errors associated with the cache miss.
313 lines
10 KiB
C
313 lines
10 KiB
C
// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously
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* This function will be initialize after FreeRTOS startup.
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* When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt,
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* cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <sdkconfig.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr.h"
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/portmacro.h"
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#include "xtensa/core-macros.h"
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#ifndef CONFIG_FREERTOS_UNICORE
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static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
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#define DPORT_CORE_STATE_IDLE 0
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#define DPORT_CORE_STATE_RUNNING 1
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static uint32_t volatile dport_core_state[portNUM_PROCESSORS]; //cpu is already run
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/* these global variables are accessed from interrupt vector, hence not declared as static */
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uint32_t volatile dport_access_start[portNUM_PROCESSORS]; //dport register could be accessed
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uint32_t volatile dport_access_end[portNUM_PROCESSORS]; //dport register is accessed over
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static uint32_t volatile dport_access_ref[portNUM_PROCESSORS]; //dport access reference
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#ifdef DPORT_ACCESS_BENCHMARK
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#define DPORT_ACCESS_BENCHMARK_STORE_NUM
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static uint32_t ccount_start[portNUM_PROCESSORS];
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static uint32_t ccount_end[portNUM_PROCESSORS];
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static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_NUM];
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static uint32_t ccount_margin_cnt;
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#endif
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static BaseType_t oldInterruptLevel[2];
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#endif // CONFIG_FREERTOS_UNICORE
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/* stall other cpu that this cpu is pending to access dport register start */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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BaseType_t intLvl = portENTER_CRITICAL_NESTED();
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int cpu_id = xPortGetCoreID();
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
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#endif
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if (dport_access_ref[cpu_id] == 0) {
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portENTER_CRITICAL_ISR(&g_dport_mux);
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oldInterruptLevel[cpu_id]=intLvl;
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dport_access_start[cpu_id] = 0;
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dport_access_end[cpu_id] = 0;
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if (cpu_id == 0) {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
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} else {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
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}
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while (!dport_access_start[cpu_id]) {};
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REG_READ(SPI_DATE_REG(3)); //just read a APB register sure that the APB-bus is idle
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}
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dport_access_ref[cpu_id]++;
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if (dport_access_ref[cpu_id] > 1) {
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/* Interrupts are already disabled by the parent, we're nested here. */
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portEXIT_CRITICAL_NESTED(intLvl);
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}
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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/* stall other cpu that this cpu is pending to access dport register end */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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int cpu_id = xPortGetCoreID();
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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if (dport_access_ref[cpu_id] == 0) {
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assert(0);
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}
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dport_access_ref[cpu_id]--;
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if (dport_access_ref[cpu_id] == 0) {
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dport_access_end[cpu_id] = 1;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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portEXIT_CRITICAL_NESTED(oldInterruptLevel[cpu_id]);
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}
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_end[cpu_id] = XTHAL_GET_CCOUNT();
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ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id];
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ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1);
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#endif
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start_wrap(void)
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{
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DPORT_STALL_OTHER_CPU_START();
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}
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void IRAM_ATTR esp_dport_access_stall_other_cpu_end_wrap(void)
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{
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DPORT_STALL_OTHER_CPU_END();
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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static void dport_access_init_core(void *arg)
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{
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int core_id = 0;
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uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
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core_id = xPortGetCoreID();
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if (core_id == 1) {
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intr_source = ETS_FROM_CPU_INTR3_SOURCE;
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}
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ESP_INTR_DISABLE(ETS_DPORT_INUM);
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intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
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ESP_INTR_ENABLE(ETS_DPORT_INUM);
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dport_access_ref[core_id] = 0;
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dport_access_start[core_id] = 0;
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dport_access_end[core_id] = 0;
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dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING;
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vTaskDelete(NULL);
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}
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#endif
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/* Defer initialisation until after scheduler is running */
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void esp_dport_access_int_init(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
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assert(res == pdTRUE);
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_pause(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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//Used in panic code: the enter_critical stuff may be messed up so we just stop everything without checking the mux.
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void IRAM_ATTR esp_dport_access_int_abort(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_resume(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_RUNNING;
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dport_core_state[1] = DPORT_CORE_STATE_RUNNING;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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/**
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* @brief Read a sequence of DPORT registers to the buffer, SMP-safe version.
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*
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* This implementation uses a method of the pre-reading of the APB register
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* before reading the register of the DPORT, without stall other CPU.
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* There is disable/enable interrupt.
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*
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* @param[out] buff_out Contains the read data.
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* @param[in] address Initial address for reading registers.
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* @param[in] num_words The number of words.
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*/
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void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words)
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{
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DPORT_INTERRUPT_DISABLE();
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for (uint32_t i = 0; i < num_words; ++i) {
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buff_out[i] = DPORT_SEQUENCE_REG_READ(address + i * 4);
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}
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DPORT_INTERRUPT_RESTORE();
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}
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/**
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* @brief Read value from register, SMP-safe version.
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*
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* This method uses the pre-reading of the APB register before reading the register of the DPORT.
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* This implementation is useful for reading DORT registers for single reading without stall other CPU.
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* There is disable/enable interrupt.
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*
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* @param reg Register address
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* @return Value
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*/
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uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
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{
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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return _DPORT_REG_READ(reg);
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#else
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uint32_t apb;
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unsigned int intLvl;
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__asm__ __volatile__ (\
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"movi %[APB], "XTSTR(0x3ff40078)"\n"\
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"rsil %[LVL], "XTSTR(3)"\n"\
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"l32i %[APB], %[APB], 0\n"\
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"l32i %[REG], %[REG], 0\n"\
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"wsr %[LVL], "XTSTR(PS)"\n"\
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"rsync\n"\
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: [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\
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: \
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: "memory" \
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);
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return reg;
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#endif
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}
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/**
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* @brief Read value from register, NOT SMP-safe version.
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*
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* This method uses the pre-reading of the APB register before reading the register of the DPORT.
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* There is not disable/enable interrupt.
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* The difference from DPORT_REG_READ() is that the user himself must disable interrupts while DPORT reading.
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* This implementation is useful for reading DORT registers in loop without stall other CPU. Note the usage example.
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* The recommended way to read registers sequentially without stall other CPU
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* is to use the method esp_dport_read_buffer(buff_out, address, num_words). It allows you to read registers in the buffer.
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*
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* \code{c}
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* // This example shows how to use it.
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* { // Use curly brackets to limit the visibility of variables in macros DPORT_INTERRUPT_DISABLE/RESTORE.
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* DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
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* for (i = 0; i < max; ++i) {
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* array[i] = esp_dport_access_sequence_reg_read(Address + i * 4); // reading DPORT registers
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* }
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* DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level
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* }
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* \endcode
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*
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* @param reg Register address
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* @return Value
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*/
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uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg)
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{
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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return _DPORT_REG_READ(reg);
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#else
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uint32_t apb;
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__asm__ __volatile__ (\
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"movi %[APB], "XTSTR(0x3ff40078)"\n"\
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"l32i %[APB], %[APB], 0\n"\
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"l32i %[REG], %[REG], 0\n"\
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: [APB]"=a"(apb), [REG]"+a"(reg)\
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: \
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: "memory" \
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);
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return reg;
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#endif
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}
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