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420aef1ffe
* Target components pull in xtensa component directly * Use CPU HAL where applicable * Remove unnecessary xtensa headers * Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no longer signed/unsigned int). Changes come from internal branch commit a6723fc
416 lines
26 KiB
C
416 lines
26 KiB
C
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include "esp_assert.h"
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#endif
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#include <esp_bit_defs.h>
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#define PRO_CPU_NUM (0)
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#define APP_CPU_NUM (1)
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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#define DR_REG_DPORT_BASE 0x3ff00000
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#define DR_REG_AES_BASE 0x3ff01000
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#define DR_REG_RSA_BASE 0x3ff02000
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#define DR_REG_SHA_BASE 0x3ff03000
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#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000
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#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000
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#define DR_REG_DPORT_END 0x3ff13FFC
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#define DR_REG_UART_BASE 0x3ff40000
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#define DR_REG_SPI1_BASE 0x3ff42000
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#define DR_REG_SPI0_BASE 0x3ff43000
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#define DR_REG_GPIO_BASE 0x3ff44000
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#define DR_REG_GPIO_SD_BASE 0x3ff44f00
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#define DR_REG_FE2_BASE 0x3ff45000
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#define DR_REG_FE_BASE 0x3ff46000
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#define DR_REG_FRC_TIMER_BASE 0x3ff47000
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#define DR_REG_RTCCNTL_BASE 0x3ff48000
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#define DR_REG_RTCIO_BASE 0x3ff48400
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#define DR_REG_SENS_BASE 0x3ff48800
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#define DR_REG_RTC_I2C_BASE 0x3ff48C00
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#define DR_REG_IO_MUX_BASE 0x3ff49000
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#define DR_REG_HINF_BASE 0x3ff4B000
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#define DR_REG_UHCI1_BASE 0x3ff4C000
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#define DR_REG_I2S_BASE 0x3ff4F000
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#define DR_REG_UART1_BASE 0x3ff50000
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#define DR_REG_BT_BASE 0x3ff51000
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#define DR_REG_I2C_EXT_BASE 0x3ff53000
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#define DR_REG_UHCI0_BASE 0x3ff54000
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#define DR_REG_SLCHOST_BASE 0x3ff55000
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#define DR_REG_RMT_BASE 0x3ff56000
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#define DR_REG_PCNT_BASE 0x3ff57000
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#define DR_REG_SLC_BASE 0x3ff58000
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#define DR_REG_LEDC_BASE 0x3ff59000
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#define DR_REG_EFUSE_BASE 0x3ff5A000
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#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
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#define DR_REG_NRX_BASE 0x3ff5CC00
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#define DR_REG_BB_BASE 0x3ff5D000
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#define DR_REG_PWM_BASE 0x3ff5E000
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#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
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#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
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#define DR_REG_RTCMEM0_BASE 0x3ff61000
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#define DR_REG_RTCMEM1_BASE 0x3ff62000
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#define DR_REG_RTCMEM2_BASE 0x3ff63000
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#define DR_REG_SPI2_BASE 0x3ff64000
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#define DR_REG_SPI3_BASE 0x3ff65000
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#define DR_REG_SYSCON_BASE 0x3ff66000
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#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */
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#define DR_REG_I2C1_EXT_BASE 0x3ff67000
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#define DR_REG_SDMMC_BASE 0x3ff68000
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#define DR_REG_EMAC_BASE 0x3ff69000
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#define DR_REG_CAN_BASE 0x3ff6B000
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#define DR_REG_PWM1_BASE 0x3ff6C000
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#define DR_REG_I2S1_BASE 0x3ff6D000
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#define DR_REG_UART2_BASE 0x3ff6E000
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#define DR_REG_PWM2_BASE 0x3ff6F000
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#define DR_REG_PWM3_BASE 0x3ff70000
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#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
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#if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM )
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#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
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#else
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#define ASSERT_IF_DPORT_REG(_r, OP)
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#endif
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//write value to register
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#define REG_WRITE(_r, _v) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
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(*(volatile uint32_t *)(_r)) = (_v); \
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})
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//read value from register
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#define REG_READ(_r) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_READ); \
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(*(volatile uint32_t *)(_r)); \
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})
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
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(*(volatile uint32_t*)(_r) & (_b)); \
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})
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
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(*(volatile uint32_t*)(_r) |= (_b)); \
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})
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
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(*(volatile uint32_t*)(_r) &= ~(_b)); \
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})
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
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(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
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})
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
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((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
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})
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
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(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
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})
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) ({ \
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ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
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})
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//write value to register
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#define WRITE_PERI_REG(addr, val) ({ \
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ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
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})
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
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})
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
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})
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
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(READ_PERI_REG(reg) & (mask)); \
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})
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
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((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
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})
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
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(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
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})
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
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((READ_PERI_REG(reg)>>(shift))&(mask)); \
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})
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#endif /* !__ASSEMBLER__ */
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//}}
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//Periheral Clock {{
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#define APB_CLK_FREQ_ROM ( 26*1000000 )
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP32_DEFAULT_CPU_FREQ_MHZ
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#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
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#define REF_CLK_FREQ ( 1000000 )
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define WDT_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
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#define SPI_CLK_DIV 4
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#define TICKS_PER_US_ROM 26 // CPU is 80MHz
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#define GPIO_MATRIX_DELAY_NS 25
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//}}
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/* Overall memory map */
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#define SOC_DROM_LOW 0x3F400000
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_DRAM_LOW 0x3FFAE000
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#define SOC_DRAM_HIGH 0x40000000
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x40064F00
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#define SOC_CACHE_PRO_LOW 0x40070000
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#define SOC_CACHE_PRO_HIGH 0x40078000
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#define SOC_CACHE_APP_LOW 0x40078000
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#define SOC_CACHE_APP_HIGH 0x40080000
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#define SOC_IRAM_LOW 0x40080000
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#define SOC_IRAM_HIGH 0x400A0000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DRAM_LOW 0x3FF80000
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#define SOC_RTC_DRAM_HIGH 0x3FF82000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define SOC_EXTRAM_DATA_LOW 0x3F800000
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#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
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#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
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//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
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#define SOC_DIRAM_IRAM_LOW 0x400A0000
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#define SOC_DIRAM_IRAM_HIGH 0x400C0000
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#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
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#define SOC_DIRAM_DRAM_HIGH 0x40000000
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// Byte order of D/IRAM regions is reversed between accessing as DRAM or IRAM
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#define SOC_DIRAM_INVERTED 1
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FFAE000
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#define SOC_DMA_HIGH 0x40000000
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// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
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#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000
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#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
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//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
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//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
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#define SOC_MEM_INTERNAL_LOW 0x3FF90000
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#define SOC_MEM_INTERNAL_HIGH 0x400C2000
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// Start (highest address) of ROM boot stack, only relevant during early boot
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#define SOC_ROM_STACK_START 0x3ffe3f20
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//Interrupt hardware source table
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//This table is decided by hardware, don't touch this.
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#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
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#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
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#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
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#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/
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#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/
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#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
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#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/
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#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/
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#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
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#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
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#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/
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#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/
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#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/
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#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/
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#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
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#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
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#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
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#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/
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#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
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#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
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#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
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#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/
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#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/
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#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
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#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
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#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
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#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
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#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
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#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
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#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
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#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
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#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/
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#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/
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#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/
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#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/
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#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/
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#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/
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#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/
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#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/
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#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/
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#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/
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#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/
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#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/
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#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/
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#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/
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#define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/
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#define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE
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#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/
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#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/
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#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/
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#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/
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#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/
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#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/
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#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
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#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/
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#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/
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#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/
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#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/
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#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/
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#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
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#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
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#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
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#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
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#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
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#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
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#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
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#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
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#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/
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#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/
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#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
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#define ETS_MAX_INTR_SOURCE 69/**< total number of interrupt sources*/
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//interrupt cpu using table, Please see the core-isa.h
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/*************************************************************************************************************
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* Intr num Level Type PRO CPU usage APP CPU uasge
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* 0 1 extern level WMAC Reserved
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* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
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* 2 1 extern level
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* 3 1 extern level
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* 4 1 extern level WBB
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* 5 1 extern level BT/BLE Controller BT/BLE Controller
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* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
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* 7 1 software BT/BLE VHCI BT/BLE VHCI
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* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
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* 9 1 extern level
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* 10 1 extern edge
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* 11 3 profiling
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* 12 1 extern level
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* 13 1 extern level
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* 14 7 nmi Reserved Reserved
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* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
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* 16 5 timer
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* 17 1 extern level
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* 18 1 extern level
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* 19 2 extern level
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* 20 2 extern level
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* 21 2 extern level
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* 22 3 extern edge
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* 23 3 extern level
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* 24 4 extern level TG1_WDT
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* 25 4 extern level CACHEERR
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* 26 5 extern level
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* 27 3 extern level Reserved Reserved
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* 28 4 extern edge DPORT ACCESS DPORT ACCESS
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* 29 3 software Reserved Reserved
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* 30 4 extern edge Reserved Reserved
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* 31 5 extern level
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*************************************************************************************************************
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*/
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//CPU0 Interrupt number reserved, not touch this.
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#define ETS_WMAC_INUM 0
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#define ETS_BT_HOST_INUM 1
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#define ETS_WBB_INUM 4
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#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
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#define ETS_FRC1_INUM 22
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#define ETS_T1_WDT_INUM 24
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#define ETS_MEMACCESS_ERR_INUM 25
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/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
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#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
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#define ETS_DPORT_INUM 28
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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#define ETS_UART0_INUM 5
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#define ETS_UART1_INUM 5
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//Other interrupt number should be managed by the user
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//Invalid interrupt for number interrupt matrix
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#define ETS_INVALID_INUM 6
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