mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
209 lines
8.9 KiB
ArmAsm
209 lines
8.9 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "portmacro.h"
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#include "freertos/FreeRTOSConfig.h"
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#include "soc/soc_caps.h"
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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#include "esp_private/hw_stack_guard.h"
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#endif
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.global port_uxInterruptNesting
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.global port_xSchedulerRunning
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.global xIsrStackTop
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.global pxCurrentTCB
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.global vTaskSwitchContext
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.global xPortSwitchFlag
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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.global xIsrStack
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.global port_offset_pxStack
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.global port_offset_pxEndOfStack
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.global esp_hw_stack_guard_monitor_stop
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.global esp_hw_stack_guard_monitor_start
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.global esp_hw_stack_guard_set_bounds
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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.section .text
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/**
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* This function makes the RTOS aware about an ISR entering. It takes the
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* current task stack pointer and places it into the pxCurrentTCB.
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* It then loads the ISR stack into sp.
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* TODO: ISR nesting code improvements ?
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*/
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.global rtos_int_enter
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.type rtos_int_enter, @function
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rtos_int_enter:
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#if CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7861
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/* preserve the return address */
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mv t1, ra
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mv t2, a0
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#endif
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/* If the scheduler is not enabled, jump directly to the ISR handler */
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#if ( configNUM_CORES > 1 )
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csrr t6, mhartid /* t6 = coreID */
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slli t6, t6, 2 /* t6 = coreID * 4 */
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la t0, port_xSchedulerRunning /* t0 = &port_xSchedulerRunning */
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add t0, t0, t6 /* t0 = &port_xSchedulerRunning[coreID] */
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lw t0, (t0) /* t0 = port_xSchedulerRunning[coreID] */
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#else
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lw t0, port_xSchedulerRunning /* t0 = port_xSchedulerRunning */
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#endif /* (configNUM_CORES > 1) */
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beq t0, zero, rtos_int_enter_end /* if (port_xSchedulerRunning[coreID] == 0) jump to rtos_int_enter_end */
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/* Increment the ISR nesting count */
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la t3, port_uxInterruptNesting /* t3 = &port_usInterruptNesting */
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#if ( configNUM_CORES > 1 )
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add t3, t3, t6 /* t3 = &port_uxInterruptNesting[coreID] // t6 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw t4, 0x0(t3) /* t4 = port_uxInterruptNesting[coreID] */
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addi t5, t4, 1 /* t5 = t4 + 1 */
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sw t5, 0x0(t3) /* port_uxInterruptNesting[coreID] = t5 */
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/* If we reached here from another low-prio ISR, i.e, port_uxInterruptNesting[coreID] > 0, then skip stack pushing to TCB */
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bne t4, zero, rtos_int_enter_end /* if (port_uxInterruptNesting[coreID] > 0) jump to rtos_int_enter_end */
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_monitor_stop(); */
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ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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/* Save the current sp in pxCurrentTCB[coreID] and load the ISR stack on to sp */
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#if ( configNUM_CORES > 1 )
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la t0, pxCurrentTCB /* t0 = &pxCurrentTCB */
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add t0, t0, t6 /* t0 = &pxCurrentTCB[coreID] // t6 already contains coreID * 4 */
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lw t0, (t0) /* t0 = pxCurrentTCB[coreID] */
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sw sp, 0x0(t0) /* pxCurrentTCB[coreID] = sp */
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la t0, xIsrStackTop /* t0 = &xIsrStackTop */
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add t0, t0, t6 /* t0 = &xIsrStackTop[coreID] // t6 already contains coreID * 4 */
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lw sp, 0x0(t0) /* sp = xIsrStackTop[coreID] */
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#else
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lw t0, pxCurrentTCB /* t0 = pxCurrentTCB */
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sw sp, 0x0(t0) /* pxCurrentTCB = sp */
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lw sp, xIsrStackTop /* sp = xIsrStackTop */
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#endif /* ( configNUM_CORES > 1 ) */
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_set_bounds(xIsrStack, xIsrStackTop); */
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la a0, xIsrStack
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mv a1, sp
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ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
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ESP_HW_STACK_GUARD_MONITOR_START_CPU0
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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rtos_int_enter_end:
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#if CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7861
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mv ra, t1
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#endif
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ret
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/**
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* Restore the stack pointer of the next task to run.
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*/
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.global rtos_int_exit
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.type rtos_int_exit, @function
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rtos_int_exit:
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/* Skip if the scheduler was not started */
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#if ( configNUM_CORES > 1 )
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csrr t1, mhartid /* t1 = coreID */
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slli t1, t1, 2 /* t1 = t1 * 4 */
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la t0, port_xSchedulerRunning /* t0 = &port_xSchedulerRunning */
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add t0, t0, t1 /* t0 = &port_xSchedulerRunning[coreID] */
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lw t0, (t0) /* t0 = port_xSchedulerRunning[coreID] */
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#else
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lw t0, port_xSchedulerRunning /* t0 = port_xSchedulerRunning */
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#endif /* ( configNUM_CORES > 1 ) */
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beq t0, zero, rtos_int_exit_end /* if (port_uxSchewdulerRunning == 0) jump to rtos_int_exit_end */
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/* Decrement interrupt nesting counter */
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la t2, port_uxInterruptNesting /* t2 = &port_uxInterruptNesting */
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#if ( configNUM_CORES > 1 )
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add t2, t2, t1 /* t2 = &port_uxInterruptNesting[coreID] // t1 already contains coreID * 4 */
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#endif
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lw t3, 0x0(t2) /* t3 = port_uxInterruptNesting[coreID] */
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/* If the interrupt nesting counter is already zero, then protect against underflow */
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beq t3, zero, isr_skip_decrement /* if (port_uxInterruptNesting[coreID] == 0) jump to isr_skip_decrement */
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addi t3, t3, -1 /* t3 = t3 - 1 */
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sw t3, 0x0(t2) /* port_uxInterruptNesting[coreID] = t3 */
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isr_skip_decrement:
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/* We may still have interrupts pending. Skip the section below and exit */
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bne t3, zero, rtos_int_exit_end /* (if port_uxInterruptNesting[coreID] > 0) jump to rtos_int_exit_end */
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/* Schedule the next task if an yield is pending */
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la t0, xPortSwitchFlag /* t0 = &xPortSwitchFlag */
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#if ( configNUM_CORES > 1 )
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add t0, t0, t1 /* t0 = &xPortSwitchFlag[coreID] // t1 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw t2, 0x0(t0) /* t2 = xPortSwitchFlag[coreID] */
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beq t2, zero, no_switch /* if (xPortSwitchFlag[coreID] == 0) jump to no_switch */
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/* Save the return address on the stack and create space on the stack for the c-routine call to schedule
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* the next task. Stack pointer for RISC-V should always be 16 byte aligned. After the switch, restore
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* the return address and sp.
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*/
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addi sp, sp, -16 /* sp = sp - 16 */
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sw ra, 0(sp) /* sp = ra */
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call vTaskSwitchContext /* vTaskSwitchContext() */
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lw ra, 0(sp) /* ra = sp */
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addi sp, sp, 16 /* sp = sp + 16 */
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/* Clear the switch pending flag */
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la t0, xPortSwitchFlag /* t0 = &xPortSwitchFlag */
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#if ( configNUM_CORES > 1 )
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/* c routine vTaskSwitchContext may change the temp registers, so we read again */
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csrr t3, mhartid /* t3 = coreID */
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slli t3, t3, 2 /* t3 = t3 * 4 */
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add t0, t0, t3 /* t0 = &xPortSwitchFlag[coreID] */
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#endif /* ( configNUM_CORES > 1 ) */
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mv t2, zero /* t2 = 0 */
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sw t2, 0x0(t0) /* xPortSwitchFlag[coreID] = t2 */
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no_switch:
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#if SOC_INT_CLIC_SUPPORTED
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/* Recover the stack of next task and prepare to exit */
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la a0, pxCurrentTCB /* a0 = &pxCurrentTCB */
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#if ( configNUM_CORES > 1 )
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csrr t3, mhartid /* t3 = coreID */
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slli t3, t3, 2 /* t3 = t3 * 4 */
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add a0, a0, t3 /* a0 = &pxCurrentTCB[coreID] */
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#endif /* ( configNUM_CORES > 1 ) */
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lw a0, (a0) /* a0 = pxCurrentTCB[coreID] */
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lw a0, 0x0(a0) /* a0 = previous sp */
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#else
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_monitor_stop(); */
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ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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/* Recover the stack of next task */
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lw t0, pxCurrentTCB
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lw sp, 0x0(t0)
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_set_bounds(pxCurrentTCB[0]->pxStack,
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* pxCurrentTCB[0]->pxEndOfStack);
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*/
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lw a0, PORT_OFFSET_PX_STACK(t0)
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lw a1, PORT_OFFSET_PX_END_OF_STACK(t0)
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ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
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/* esp_hw_stack_guard_monitor_start(); */
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ESP_HW_STACK_GUARD_MONITOR_START_CPU0
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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#endif /* SOC_INT_CLIC_SUPPORTED */
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rtos_int_exit_end:
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ret
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