mirror of
https://github.com/espressif/esp-idf.git
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320 lines
8.9 KiB
C
320 lines
8.9 KiB
C
/**
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: SDM Configure Registers */
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/** Type of sigmadeltan register
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* Duty Cycle Configure Register of SDMn
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*/
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typedef union {
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struct {
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/** duty : R/W; bitpos: [7:0]; default: 0;
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* This field is used to configure the duty cycle of sigma delta modulation output.
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*/
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uint32_t duty:8;
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/** prescale : R/W; bitpos: [15:8]; default: 255;
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* This field is used to set a divider value to divide APB clock.
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*/
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uint32_t prescale:8;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} gpio_sigmadelta_chn_reg_t;
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/** Type of sigmadelta_misc register
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* MISC Register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:30;
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/** function_clk_en : R/W; bitpos: [30]; default: 0;
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* Clock enable bit of sigma delta modulation.
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*/
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uint32_t function_clk_en:1;
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/** spi_swap : R/W; bitpos: [31]; default: 0;
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* Reserved.
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*/
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uint32_t spi_swap:1;
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};
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uint32_t val;
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} gpio_sigmadelta_misc_reg_t;
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/** Group: Clock gate Register */
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/** Type of clock_gate register
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* Clock Gating Configure Register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 0;
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* Clock enable bit of configuration registers for sigma delta modulation.
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_sigmadelta_clock_gate_reg_t;
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/** Group: Configure Registers */
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/** Type of pad_comp_config register
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* PAD Compare configure Register
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*/
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typedef union {
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struct {
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/** xpd_comp : R/W; bitpos: [0]; default: 0;
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* Pad compare enable bit.
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*/
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uint32_t xpd_comp:1;
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/** mode_comp : R/W; bitpos: [1]; default: 0;
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* 1 to enable external reference from PAD[10]. 0 to enable internal reference,
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* meanwhile PAD[10] can be used as a regular GPIO.
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*/
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uint32_t mode_comp:1;
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/** dref_comp : R/W; bitpos: [4:2]; default: 0;
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* internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
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*/
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uint32_t dref_comp:3;
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/** zero_det_mode : R/W; bitpos: [6:5]; default: 0;
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* Zero Detect mode select.
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*/
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uint32_t zero_det_mode:2;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} gpio_pad_comp_config_reg_t;
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/** Type of pad_comp_filter register
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* Zero Detect filter Register
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*/
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typedef union {
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struct {
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/** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 0;
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* Zero Detect filter cycle length
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*/
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uint32_t zero_det_filter_cnt:32;
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};
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uint32_t val;
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} gpio_pad_comp_filter_reg_t;
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/** Group: Glitch filter Configure Registers */
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/** Type of glitch_filter_chn register
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* Glitch Filter Configure Register of Channeln
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*/
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typedef union {
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struct {
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/** filter_chn_en : R/W; bitpos: [0]; default: 0;
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* Glitch Filter channel enable bit.
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*/
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uint32_t filter_chn_en:1;
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/** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
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* Glitch Filter input io number.
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*/
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uint32_t filter_chn_input_io_num:6;
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/** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0;
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* Glitch Filter window threshold.
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*/
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uint32_t filter_chn_window_thres:6;
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/** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0;
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* Glitch Filter window width.
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*/
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uint32_t filter_chn_window_width:6;
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uint32_t reserved_19:13;
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};
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uint32_t val;
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} gpio_glitch_filter_chn_reg_t;
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/** Group: Etm Configure Registers */
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/** Type of etm_event_chn_cfg register
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* Etm Config register of Channeln
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*/
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typedef union {
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struct {
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/** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0;
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* Etm event channel select gpio.
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*/
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uint32_t etm_chn_event_sel:5;
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uint32_t reserved_5:2;
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/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
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* Etm event send enable bit.
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*/
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uint32_t etm_chn_event_en:1;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} gpio_etm_event_chn_cfg_reg_t;
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/** Type of etm_task_p0_cfg register
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* Etm Configure Register to decide which GPIO been chosen
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*/
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typedef union {
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struct {
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/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
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* Enable bit of GPIO response etm task.
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*/
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uint32_t etm_task_gpio0_en:1;
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/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
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* GPIO choose a etm task channel.
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*/
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uint32_t etm_task_gpio0_sel:3;
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uint32_t reserved_4:4;
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/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
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* Enable bit of GPIO response etm task.
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*/
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uint32_t etm_task_gpio1_en:1;
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/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
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* GPIO choose a etm task channel.
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*/
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uint32_t etm_task_gpio1_sel:3;
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uint32_t reserved_12:4;
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/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
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* Enable bit of GPIO response etm task.
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*/
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uint32_t etm_task_gpio2_en:1;
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/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
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* GPIO choose a etm task channel.
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*/
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uint32_t etm_task_gpio2_sel:3;
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uint32_t reserved_20:4;
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/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
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* Enable bit of GPIO response etm task.
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*/
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uint32_t etm_task_gpio3_en:1;
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/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
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* GPIO choose a etm task channel.
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*/
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uint32_t etm_task_gpio3_sel:3;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} gpio_etm_task_pn_cfg_reg_t;
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/** Group: Interrupt Registers */
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/** Type of int_raw register
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* GPIOSD interrupt raw register
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*/
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typedef union {
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struct {
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/** pad_comp_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
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* Pad compare raw interrupt
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*/
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uint32_t pad_comp_int_raw:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_ext_int_raw_reg_t;
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/** Type of int_st register
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* GPIOSD interrupt masked register
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*/
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typedef union {
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struct {
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/** pad_comp_int_st : RO; bitpos: [0]; default: 0;
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* Pad compare masked interrupt
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*/
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uint32_t pad_comp_int_st:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_ext_int_st_reg_t;
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/** Type of int_ena register
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* GPIOSD interrupt enable register
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*/
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typedef union {
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struct {
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/** pad_comp_int_ena : R/W; bitpos: [0]; default: 0;
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* Pad compare interrupt enable
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*/
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uint32_t pad_comp_int_ena:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_ext_int_ena_reg_t;
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/** Type of int_clr register
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* GPIOSD interrupt clear register
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*/
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typedef union {
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struct {
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/** pad_comp_int_clr : WT; bitpos: [0]; default: 0;
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* Pad compare interrupt clear
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*/
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uint32_t pad_comp_int_clr:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_ext_int_clr_reg_t;
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/** Group: Version Register */
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/** Type of version register
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* Version Control Register
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*/
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typedef union {
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struct {
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/** gpio_sd_date : R/W; bitpos: [27:0]; default: 35684640;
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* Version control register.
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*/
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uint32_t gpio_sd_date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} gpio_ext_version_reg_t;
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typedef struct gpio_sd_dev_t {
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volatile gpio_sigmadelta_chn_reg_t channel[4];
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uint32_t reserved_010[4];
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volatile gpio_sigmadelta_clock_gate_reg_t clock_gate;
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volatile gpio_sigmadelta_misc_reg_t misc;
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} gpio_sd_dev_t;
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typedef struct {
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volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8];
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} gpio_glitch_filter_dev_t;
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typedef struct {
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volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
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uint32_t reserved_080[8];
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volatile gpio_etm_task_pn_cfg_reg_t etm_task_pn_cfg[7];
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} gpio_etm_dev_t;
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typedef struct {
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volatile gpio_sd_dev_t sigma_delta;
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volatile gpio_pad_comp_config_reg_t pad_comp_config;
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volatile gpio_pad_comp_filter_reg_t pad_comp_filter;
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volatile gpio_glitch_filter_dev_t glitch_filter;
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uint32_t reserved_050[4];
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volatile gpio_etm_dev_t etm;
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uint32_t reserved_0bc[9];
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volatile gpio_ext_int_raw_reg_t int_raw;
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volatile gpio_ext_int_st_reg_t int_st;
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volatile gpio_ext_int_ena_reg_t int_ena;
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volatile gpio_ext_int_clr_reg_t int_clr;
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uint32_t reserved_0f0[3];
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volatile gpio_ext_version_reg_t version;
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} gpio_ext_dev_t;
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extern gpio_sd_dev_t SDM;
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extern gpio_glitch_filter_dev_t GLITCH_FILTER;
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extern gpio_etm_dev_t GPIO_ETM;
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extern gpio_ext_dev_t GPIO_EXT;
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#ifndef __cplusplus
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_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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