mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
a8b1475fe7
This commit mainly targets the ESP32-P4. It adds supports for coprocessors on RISC-V based targets. The coprocessor save area, describing the used coprocessors is stored at the end of the stack of each task (highest address) whereas each coprocessor save area is allocated at the beginning of the task (lowest address). The context of each coprocessor is saved lazily, by the task that want to use it.
777 lines
28 KiB
C
777 lines
28 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <string.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_chip_info.h"
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#include "esp_efuse.h"
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#include "esp_private/cache_err_int.h"
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#include "esp_clk_internal.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_caps.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/dport_reg.h"
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#include "esp32/rtc.h"
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#include "esp32/rom/cache.h"
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#include "esp32/rom/secure_boot.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rtc.h"
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#include "esp32s2/rom/cache.h"
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#include "esp32s2/rom/secure_boot.h"
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#include "esp32s2/memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rtc.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/rom/secure_boot.h"
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#include "esp_memprot.h"
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#include "soc/assist_debug_reg.h"
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#include "soc/system_reg.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "hal/cache_hal.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rtc.h"
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/rom/secure_boot.h"
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#include "esp_memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rtc.h"
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#include "esp32c6/rom/cache.h"
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#include "esp_memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rtc.h"
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#include "esp32h2/rom/cache.h"
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#include "esp_memprot.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rtc.h"
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#include "esp32c2/rom/cache.h"
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#include "esp32c2/rom/rtc.h"
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#include "esp32c2/rom/secure_boot.h"
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#elif CONFIG_IDF_TARGET_ESP32P4
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#include "esp32p4/rtc.h"
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#include "soc/hp_sys_clkrst_reg.h"
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#include "soc/interrupt_core0_reg.h"
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#include "soc/interrupt_core1_reg.h"
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#endif
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#include "esp_private/esp_mmu_map_private.h"
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#if CONFIG_SPIRAM
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#include "esp_psram.h"
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#include "esp_private/mmu_psram_flash.h"
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#include "esp_private/esp_psram_extram.h"
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#endif
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_flash.h"
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#include "esp_private/crosscore_int.h"
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#include "esp_flash_encrypt.h"
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#include "esp_private/sleep_gpio.h"
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#include "hal/wdt_hal.h"
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#include "soc/rtc.h"
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#include "hal/cache_ll.h"
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#include "hal/efuse_ll.h"
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#include "soc/periph_defs.h"
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#include "esp_cpu.h"
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#include "esp_private/esp_clk.h"
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#include "spi_flash_mmap.h"
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#if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
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#include "esp_private/trax.h"
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#endif
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#include "bootloader_mem.h"
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#if CONFIG_APP_BUILD_TYPE_RAM
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#include "esp_rom_spiflash.h"
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#include "bootloader_init.h"
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#endif // CONFIG_APP_BUILD_TYPE_RAM
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//This dependency will be removed in the future
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#include "soc/ext_mem_defs.h"
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#include "esp_private/startup_internal.h"
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#include "esp_private/system_internal.h"
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extern int _bss_start;
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extern int _bss_end;
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extern int _rtc_bss_start;
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extern int _rtc_bss_end;
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#if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
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extern int _bss_bt_start;
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extern int _bss_bt_end;
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#endif // CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
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extern int _instruction_reserved_start;
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extern int _instruction_reserved_end;
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extern int _rodata_reserved_start;
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extern int _rodata_reserved_end;
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extern int _vector_table;
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#if SOC_INT_CLIC_SUPPORTED
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extern int _mtvt_table;
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#endif
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static const char *TAG = "cpu_start";
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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extern int _ext_ram_bss_start;
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extern int _ext_ram_bss_end;
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#endif
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#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
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extern int _iram_bss_start;
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extern int _iram_bss_end;
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#endif
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
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static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
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static volatile bool s_resume_cores;
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#endif
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static void core_intr_matrix_clear(void)
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{
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uint32_t core_id = esp_cpu_get_core_id();
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for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
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#if CONFIG_IDF_TARGET_ESP32P4
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if (core_id == 0) {
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REG_WRITE(INTERRUPT_CORE0_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
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} else {
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REG_WRITE(INTERRUPT_CORE1_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
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}
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#else
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esp_rom_route_intr_matrix(core_id, i, ETS_INVALID_INUM);
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#endif // CONFIG_IDF_TARGET_ESP32P4
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}
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#if SOC_INT_CLIC_SUPPORTED
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for (int i = 0; i < 32; i++) {
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/* Set all the CPU interrupt lines to vectored by default, as it is on other RISC-V targets */
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esprv_intc_int_set_vectored(i, true);
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}
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#endif // SOC_INT_CLIC_SUPPORTED
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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void startup_resume_other_cores(void)
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{
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s_resume_cores = true;
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}
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void IRAM_ATTR call_start_cpu1(void)
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{
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#ifdef __riscv
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// Configure the global pointer register
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// (This should be the first thing IDF app does, as any other piece of code could be
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// relaxed by the linker to access something relative to __global_pointer$)
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__asm__ __volatile__ (
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".option push\n"
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".option norelax\n"
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"la gp, __global_pointer$\n"
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".option pop"
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);
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#endif //#ifdef __riscv
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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esp_cpu_branch_prediction_enable();
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#endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED
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esp_cpu_intr_set_ivt_addr(&_vector_table);
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#if SOC_INT_CLIC_SUPPORTED
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/* When hardware vectored interrupts are enabled in CLIC,
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* the CPU jumps to this base address + 4 * interrupt_id.
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*/
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esp_cpu_intr_set_mtvt_addr(&_mtvt_table);
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#endif
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ets_set_appcpu_boot_addr(0);
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bootloader_init_mem();
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#if CONFIG_ESP_CONSOLE_NONE
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esp_rom_install_channel_putc(1, NULL);
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esp_rom_install_channel_putc(2, NULL);
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#else // CONFIG_ESP_CONSOLE_NONE
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esp_rom_install_uart_printf();
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esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
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DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
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#elif CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7688
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#else
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REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1);
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REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1);
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#endif
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s_cpu_up[1] = true;
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ESP_EARLY_LOGD(TAG, "App cpu up");
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// Clear interrupt matrix for APP CPU core
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core_intr_matrix_clear();
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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//Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
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//has started, but it isn't active *on this CPU* yet.
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esp_cache_err_int_init();
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#endif
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#if (CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP32_TRAX_TWOBANKS) || \
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(CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP32S3_TRAX_TWOBANKS)
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trax_start_trace(TRAX_DOWNCOUNT_WORDS);
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#endif
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s_cpu_inited[1] = true;
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while (!s_resume_cores) {
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esp_rom_delay_us(100);
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}
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SYS_STARTUP_FN();
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}
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static void start_other_core(void)
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{
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esp_chip_info_t chip_info;
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esp_chip_info(&chip_info);
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// If not the single core variant of a target - check this since there is
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// no separate soc_caps.h for the single core variant.
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if (!(chip_info.cores > 1)) {
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ESP_EARLY_LOGE(TAG, "Running on single core variant of a chip, but app is built with multi-core support.");
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ESP_EARLY_LOGE(TAG, "Check that CONFIG_FREERTOS_UNICORE is enabled in menuconfig");
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abort();
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}
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ESP_EARLY_LOGD(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
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#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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Cache_Flush(1);
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Cache_Read_Enable(1);
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#endif // #if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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esp_cpu_unstall(1);
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// Enable clock and reset APP CPU. Note that OpenOCD may have already
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// enabled clock and taken APP CPU out of reset. In this case don't reset
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// APP CPU again, as that will clear the breakpoints which may have already
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// been set.
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#if CONFIG_IDF_TARGET_ESP32
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if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
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DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
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DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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}
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#elif CONFIG_IDF_TARGET_ESP32S3
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if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
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REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
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REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
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}
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#elif CONFIG_IDF_TARGET_ESP32P4
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if (!REG_GET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN)) {
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REG_SET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
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}
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if(REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)){
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REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
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}
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#endif
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ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
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bool cpus_up = false;
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while (!cpus_up) {
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cpus_up = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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cpus_up &= s_cpu_up[i];
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}
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esp_rom_delay_us(100);
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}
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}
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#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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// This function is needed to make the multicore app runnable on a unicore bootloader (built with FREERTOS UNICORE).
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// It does some cache settings for other CPUs.
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void IRAM_ATTR do_multicore_settings(void)
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{
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// We intentionally do not check the cache settings before changing them,
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// because it helps to get the application to run on older bootloaders.
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#ifdef CONFIG_IDF_TARGET_ESP32
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if (!efuse_ll_get_disable_app_cpu()) {
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Cache_Read_Disable(1);
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Cache_Flush(1);
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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// We do not enable cache for CPU1 now because it will be done later in start_other_core().
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}
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#endif
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cache_bus_mask_t cache_bus_mask_core0 = cache_ll_l1_get_enabled_bus(0);
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#ifndef CONFIG_IDF_TARGET_ESP32
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// 1. disable the cache before changing its settings.
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cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
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#endif
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for (unsigned core = 1; core < SOC_CPU_CORES_NUM; core++) {
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// 2. change cache settings. All cores must have the same settings.
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cache_ll_l1_enable_bus(core, cache_bus_mask_core0);
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}
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#ifndef CONFIG_IDF_TARGET_ESP32
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// 3. enable the cache after changing its settings.
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cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
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#endif
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}
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#endif // !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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void IRAM_ATTR call_start_cpu0(void)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
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#else
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soc_reset_reason_t __attribute__((unused)) rst_reas[1];
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#endif
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#ifdef __riscv
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if (esp_cpu_dbgr_is_attached()) {
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/* Let debugger some time to detect that target started, halt it, enable ebreaks and resume.
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500ms should be enough. */
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for (uint32_t ms_num = 0; ms_num < 2; ms_num++) {
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esp_rom_delay_us(100000);
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}
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}
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// Configure the global pointer register
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// (This should be the first thing IDF app does, as any other piece of code could be
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// relaxed by the linker to access something relative to __global_pointer$)
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__asm__ __volatile__ (
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".option push\n"
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".option norelax\n"
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"la gp, __global_pointer$\n"
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".option pop"
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);
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#endif
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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esp_cpu_branch_prediction_enable();
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#endif
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// Move exception vectors to IRAM
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esp_cpu_intr_set_ivt_addr(&_vector_table);
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#if SOC_INT_CLIC_SUPPORTED
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/* When hardware vectored interrupts are enabled in CLIC,
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* the CPU jumps to this base address + 4 * interrupt_id.
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*/
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esp_cpu_intr_set_mtvt_addr(&_mtvt_table);
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#endif
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rst_reas[0] = esp_rom_get_reset_reason(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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rst_reas[1] = esp_rom_get_reset_reason(1);
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#endif
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//Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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#if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
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// Clear Bluetooth bss
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memset(&_bss_bt_start, 0, (&_bss_bt_end - &_bss_bt_start) * sizeof(_bss_bt_start));
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#endif // CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
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#if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)
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// Clear IRAM BSS
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memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start));
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#endif
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#if SOC_RTC_FAST_MEM_SUPPORTED || SOC_RTC_SLOW_MEM_SUPPORTED
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/* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
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if (rst_reas[0] != RESET_REASON_CORE_DEEP_SLEEP) {
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memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
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}
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#endif
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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ESP_EARLY_LOGI(TAG, "Unicore app");
|
|
#else
|
|
ESP_EARLY_LOGI(TAG, "Multicore app");
|
|
#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
|
// It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
|
|
do_multicore_settings();
|
|
#endif // !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
|
#endif
|
|
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
|
|
// When the APP is loaded into ram for execution, some hardware initialization behaviors
|
|
// in the bootloader are still necessary
|
|
#if CONFIG_APP_BUILD_TYPE_RAM
|
|
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
|
|
esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
|
|
#else
|
|
esp_rom_spiflash_attach(0, false);
|
|
#endif
|
|
#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
bootloader_init();
|
|
#endif //#if CONFIG_APP_BUILD_TYPE_RAM
|
|
|
|
#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
|
|
// from panic handler we can be reset by RWDT or TG0WDT
|
|
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0
|
|
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
|
|| rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0
|
|
#endif
|
|
) {
|
|
wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
|
|
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
|
wdt_hal_disable(&rtc_wdt_ctx);
|
|
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
|
}
|
|
#endif
|
|
|
|
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
|
/* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
|
|
extern void esp_config_instruction_cache_mode(void);
|
|
esp_config_instruction_cache_mode();
|
|
|
|
/* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache.
|
|
Configure the mode of data : cache size, cache associated ways, cache line size.
|
|
Enable data cache, so if we don't use SPIRAM, it just works. */
|
|
extern void esp_config_data_cache_mode(void);
|
|
esp_config_data_cache_mode();
|
|
Cache_Enable_DCache(0);
|
|
#endif
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32S3
|
|
/* Configure the mode of instruction cache : cache size, cache line size. */
|
|
extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
|
|
rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
|
|
|
|
/* If we need use SPIRAM, we should use data cache.
|
|
Configure the mode of data : cache size, cache line size.*/
|
|
Cache_Suspend_DCache();
|
|
extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
|
|
rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
|
|
Cache_Resume_DCache(0);
|
|
#endif // CONFIG_IDF_TARGET_ESP32S3
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32P4
|
|
//TODO: IDF-5670, add cache init API
|
|
extern void esp_config_l2_cache_mode(void);
|
|
esp_config_l2_cache_mode();
|
|
#endif
|
|
if (esp_efuse_check_errors() != ESP_OK) {
|
|
esp_restart();
|
|
}
|
|
|
|
#if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
|
|
#if CONFIG_APP_BUILD_TYPE_ELF_RAM
|
|
// For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data
|
|
// are all in internal RAM. If the RAM loadable ELF has any requirement to memory map the
|
|
// external flash then it should use flash or partition mmap APIs.
|
|
uint32_t cache_mmu_irom_size = 0;
|
|
__attribute__((unused)) uint32_t cache_mmu_drom_size = 0;
|
|
#else // CONFIG_APP_BUILD_TYPE_ELF_RAM
|
|
uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start;
|
|
uint32_t cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
|
|
|
|
uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start;
|
|
__attribute__((unused)) uint32_t cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
|
|
#endif // !CONFIG_APP_BUILD_TYPE_ELF_RAM
|
|
|
|
/* Configure the Cache MMU size for instruction and rodata in flash. */
|
|
Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
|
|
#endif // ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
|
|
|
|
#if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
|
|
bool efuse_opflash_en = efuse_ll_get_flash_type();
|
|
if (!efuse_opflash_en) {
|
|
ESP_EARLY_LOGE(TAG, "Octal Flash option selected, but EFUSE not configured!");
|
|
abort();
|
|
}
|
|
#endif
|
|
esp_mspi_pin_init();
|
|
// For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors.
|
|
// So we have to read it here in SPI mode, before entering the OPI mode.
|
|
bootloader_flash_update_id();
|
|
/**
|
|
* This function initialise the Flash chip to the user-defined settings.
|
|
*
|
|
* In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to
|
|
* different chips.
|
|
* In this stage, we re-configure the Flash (and MSPI) to required configuration
|
|
*/
|
|
spi_flash_init_chip_state();
|
|
#if SOC_MEMSPI_SRC_FREQ_120M
|
|
mspi_timing_flash_tuning();
|
|
#endif
|
|
|
|
esp_mmu_map_init();
|
|
|
|
#if CONFIG_SPIRAM_BOOT_INIT
|
|
if (esp_psram_init() != ESP_OK) {
|
|
#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
|
|
ESP_EARLY_LOGE(TAG, "Failed to init external RAM, needed for external .bss segment");
|
|
abort();
|
|
#endif
|
|
|
|
#if CONFIG_SPIRAM_IGNORE_NOTFOUND
|
|
ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
|
|
#else
|
|
ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
|
|
abort();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
|
|
bootloader_init_mem();
|
|
|
|
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
|
s_cpu_up[0] = true;
|
|
#endif
|
|
|
|
ESP_EARLY_LOGD(TAG, "Pro cpu up");
|
|
|
|
#if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
|
|
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
|
start_other_core();
|
|
#else
|
|
ESP_EARLY_LOGI(TAG, "Single core mode");
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core
|
|
#elif CONFIG_IDF_TARGET_ESP32S3
|
|
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
|
|
#if SOC_APPCPU_HAS_CLOCK_GATING_BUG
|
|
/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETING
|
|
signals to ensure that the App core stops running in single-core mode. */
|
|
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
|
|
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
|
|
#endif
|
|
#endif // CONFIG_IDF_TARGET_ESP32
|
|
#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
|
#endif // SOC_CPU_CORES_NUM > 1
|
|
|
|
#if CONFIG_SPIRAM_MEMTEST
|
|
if (esp_psram_is_initialized()) {
|
|
bool ext_ram_ok = esp_psram_extram_test();
|
|
if (!ext_ram_ok) {
|
|
ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
|
|
abort();
|
|
}
|
|
}
|
|
#endif //CONFIG_SPIRAM_MEMTEST
|
|
|
|
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
//TODO: IDF-5023, replace with MMU driver
|
|
#if CONFIG_IDF_TARGET_ESP32S3
|
|
int s_instr_flash2spiram_off = 0;
|
|
int s_rodata_flash2spiram_off = 0;
|
|
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
|
|
s_instr_flash2spiram_off = instruction_flash2spiram_offset();
|
|
#endif
|
|
#if CONFIG_SPIRAM_RODATA
|
|
s_rodata_flash2spiram_off = rodata_flash2spiram_offset();
|
|
#endif
|
|
Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t), \
|
|
cache_mmu_drom_size / sizeof(uint32_t), \
|
|
(uint32_t)&_rodata_reserved_start, \
|
|
(uint32_t)&_rodata_reserved_end, \
|
|
s_instr_flash2spiram_off, \
|
|
s_rodata_flash2spiram_off);
|
|
#endif // CONFIG_IDF_TARGET_ESP32S3
|
|
|
|
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP || \
|
|
CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
|
|
uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0;
|
|
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP
|
|
icache_wrap_enable = 1;
|
|
#endif
|
|
#if CONFIG_ESP32S2_DATA_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
|
|
dcache_wrap_enable = 1;
|
|
#endif
|
|
extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
|
|
esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
|
|
#endif
|
|
|
|
#if CONFIG_ESP32S3_DATA_CACHE_16KB
|
|
Cache_Invalidate_DCache_All();
|
|
Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
|
|
#endif
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32C2
|
|
// TODO : IDF-5020
|
|
#if CONFIG_ESP32C2_INSTRUCTION_CACHE_WRAP
|
|
extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable);
|
|
esp_enable_cache_wrap(1);
|
|
#endif
|
|
#endif
|
|
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
|
|
#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
|
|
memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
|
|
#endif
|
|
|
|
//Enable trace memory and immediately start trace.
|
|
#if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
|
|
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3
|
|
#if CONFIG_ESP32_TRAX_TWOBANKS || CONFIG_ESP32S3_TRAX_TWOBANKS
|
|
trax_enable(TRAX_ENA_PRO_APP);
|
|
#else
|
|
trax_enable(TRAX_ENA_PRO);
|
|
#endif
|
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
|
trax_enable(TRAX_ENA_PRO);
|
|
#endif
|
|
trax_start_trace(TRAX_DOWNCOUNT_WORDS);
|
|
#endif // CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
|
|
|
|
esp_clk_init();
|
|
esp_perip_clk_init();
|
|
|
|
// Now that the clocks have been set-up, set the startup time from RTC
|
|
// and default RTC-backed system time provider.
|
|
g_startup_time = esp_rtc_get_time_us();
|
|
|
|
// Clear interrupt matrix for PRO CPU core
|
|
core_intr_matrix_clear();
|
|
|
|
#ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
|
|
#ifdef CONFIG_ESP_CONSOLE_UART
|
|
uint32_t clock_hz = esp_clk_apb_freq();
|
|
#if ESP_ROM_UART_CLK_IS_XTAL
|
|
clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM
|
|
#endif
|
|
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
|
|
|
|
// In a single thread mode, the freertos is not started yet. So don't have to use a critical section.
|
|
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
|
|
esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
|
|
#endif
|
|
#endif
|
|
|
|
#if !CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-7529
|
|
// Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins
|
|
if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
|
|
esp_deep_sleep_wakeup_io_reset();
|
|
}
|
|
#endif //#if !CONFIG_IDF_TARGET_ESP32P4
|
|
|
|
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
esp_cache_err_int_init();
|
|
#endif
|
|
|
|
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST
|
|
// Memprot cannot be locked during OS startup as the lock-on prevents any PMS changes until a next reboot
|
|
// If such a situation appears, it is likely an malicious attempt to bypass the system safety setup -> print error & reset
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
|
if (esp_memprot_is_locked_any()) {
|
|
#else
|
|
bool is_locked = false;
|
|
if (esp_mprot_is_conf_locked_any(&is_locked) != ESP_OK || is_locked) {
|
|
#endif
|
|
ESP_EARLY_LOGE(TAG, "Memprot feature locked after the system reset! Potential safety corruption, rebooting.");
|
|
esp_restart_noos();
|
|
}
|
|
|
|
//default configuration of PMS Memprot
|
|
esp_err_t memp_err = ESP_OK;
|
|
#if CONFIG_IDF_TARGET_ESP32S2 //specific for ESP32S2 unless IDF-3024 is merged
|
|
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
|
|
memp_err = esp_memprot_set_prot(PANIC_HNDL_ON, MEMPROT_LOCK, NULL);
|
|
#else
|
|
memp_err = esp_memprot_set_prot(PANIC_HNDL_ON, MEMPROT_UNLOCK, NULL);
|
|
#endif
|
|
#else //CONFIG_IDF_TARGET_ESP32S2 specific end
|
|
esp_memp_config_t memp_cfg = ESP_MEMPROT_DEFAULT_CONFIG();
|
|
#if !CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
|
|
memp_cfg.lock_feature = false;
|
|
#endif
|
|
memp_err = esp_mprot_set_prot(&memp_cfg);
|
|
#endif //other IDF_TARGETS end
|
|
|
|
if (memp_err != ESP_OK) {
|
|
ESP_EARLY_LOGE(TAG, "Failed to set Memprot feature (0x%08X: %s), rebooting.", memp_err, esp_err_to_name(memp_err));
|
|
esp_restart_noos();
|
|
}
|
|
#endif //CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST
|
|
|
|
// Read the application binary image header. This will also decrypt the header if the image is encrypted.
|
|
__attribute__((unused)) esp_image_header_t fhdr = {0};
|
|
#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO;
|
|
fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2;
|
|
fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB;
|
|
|
|
bootloader_flash_unlock();
|
|
#else
|
|
// This assumes that DROM is the first segment in the application binary, i.e. that we can read
|
|
// the binary header through cache by accessing SOC_DROM_LOW address.
|
|
hal_memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr));
|
|
|
|
#endif // CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
|
|
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
#if !CONFIG_SPIRAM_BOOT_INIT
|
|
// If psram is uninitialized, we need to improve some flash configuration.
|
|
bootloader_flash_clock_config(&fhdr);
|
|
bootloader_flash_gpio_config(&fhdr);
|
|
bootloader_flash_dummy_config(&fhdr);
|
|
bootloader_flash_cs_timing_config();
|
|
#endif //!CONFIG_SPIRAM_BOOT_INIT
|
|
#endif //CONFIG_IDF_TARGET_ESP32
|
|
|
|
#if CONFIG_SPI_FLASH_SIZE_OVERRIDE
|
|
int app_flash_size = esp_image_get_flash_size(fhdr.spi_size);
|
|
if (app_flash_size < 1 * 1024 * 1024) {
|
|
ESP_EARLY_LOGE(TAG, "Invalid flash size in app image header.");
|
|
abort();
|
|
}
|
|
bootloader_flash_update_size(app_flash_size);
|
|
#endif //CONFIG_SPI_FLASH_SIZE_OVERRIDE
|
|
#endif //!CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
|
|
|
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
|
s_cpu_inited[0] = true;
|
|
|
|
volatile bool cpus_inited = false;
|
|
|
|
while (!cpus_inited) {
|
|
cpus_inited = true;
|
|
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
|
|
cpus_inited &= s_cpu_inited[i];
|
|
}
|
|
esp_rom_delay_us(100);
|
|
}
|
|
#endif
|
|
|
|
SYS_STARTUP_FN();
|
|
}
|