LonerDan 1d0442bf99 fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V ... According to the ESP32-S2/S3 TRM, the output pin's mode is set in the RTC_GPIO_PINn_REG by programming the RTC_GPIO_PINn_PAD_DRIVER bit. The current ULP RISC-V RTCIO driver however, incorrectly programs the RTC_IO_TOUCH_PADn_REG register field RTC_IO_TOUCH_PADn_DRV. This commit fixes the bug.		2024-06-19 09:02:37 +02:00
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include	ulp: fix missing cpp header guard	2022-08-01 10:19:32 +08:00
ulp_core	fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V	2024-06-19 09:02:37 +02:00
ulp_riscv_adc.c	esp_adc: move adc common hw related code into esp_hw_support	2022-07-28 03:49:48 +00:00
ulp_riscv.c	ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2	2023-01-02 14:21:24 +01:00