mirror of
https://github.com/espressif/esp-idf.git
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656 lines
17 KiB
C
656 lines
17 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Register */
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/** Type of conf0 register
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* a
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*/
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typedef union {
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struct {
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/** tx_rst : R/W; bitpos: [0]; default: 0;
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* Write 1 then write 0 to this bit to reset decode state machine.
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*/
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uint32_t tx_rst:1;
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/** rx_rst : R/W; bitpos: [1]; default: 0;
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* Write 1 then write 0 to this bit to reset encode state machine.
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*/
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uint32_t rx_rst:1;
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/** uart0_ce : R/W; bitpos: [2]; default: 0;
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* Set this bit to link up HCI and UART0.
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*/
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uint32_t uart0_ce:1;
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/** uart1_ce : R/W; bitpos: [3]; default: 0;
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* Set this bit to link up HCI and UART1.
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*/
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uint32_t uart1_ce:1;
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uint32_t reserved_4:1;
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/** seper_en : R/W; bitpos: [5]; default: 1;
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* Set this bit to separate the data frame using a special char.
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*/
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uint32_t seper_en:1;
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/** head_en : R/W; bitpos: [6]; default: 1;
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* Set this bit to encode the data packet with a formatting header.
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*/
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uint32_t head_en:1;
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/** crc_rec_en : R/W; bitpos: [7]; default: 1;
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* Set this bit to enable UHCI to receive the 16 bit CRC.
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*/
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uint32_t crc_rec_en:1;
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/** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
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* If this bit is set to 1 UHCI will end the payload receiving process when UART has
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* been in idle state.
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*/
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uint32_t uart_idle_eof_en:1;
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/** len_eof_en : R/W; bitpos: [9]; default: 1;
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* If this bit is set to 1 UHCI decoder receiving payload data is end when the
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* receiving byte count has reached the specified value. The value is payload length
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* indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
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* configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
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* receiving payload data is end when 0xc0 is received.
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*/
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uint32_t len_eof_en:1;
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/** encode_crc_en : R/W; bitpos: [10]; default: 1;
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* Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
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* end of the payload.
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*/
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uint32_t encode_crc_en:1;
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/** clk_en : R/W; bitpos: [11]; default: 0;
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* 1'b1: Force clock on for register. 1'b0: Support clock only when application writes
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* registers.
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*/
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uint32_t clk_en:1;
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/** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
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* If this bit is set to 1 UHCI will end payload receive process when NULL frame is
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* received by UART.
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*/
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uint32_t uart_rx_brk_eof_en:1;
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uint32_t reserved_13:19;
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};
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uint32_t val;
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} uhci_conf0_reg_t;
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/** Type of conf1 register
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* a
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*/
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typedef union {
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struct {
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/** check_sum_en : R/W; bitpos: [0]; default: 1;
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* a
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*/
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uint32_t check_sum_en:1;
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/** check_seq_en : R/W; bitpos: [1]; default: 1;
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* a
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*/
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uint32_t check_seq_en:1;
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/** crc_disable : R/W; bitpos: [2]; default: 0;
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* a
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*/
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uint32_t crc_disable:1;
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/** save_head : R/W; bitpos: [3]; default: 0;
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* a
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*/
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uint32_t save_head:1;
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/** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
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* a
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*/
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uint32_t tx_check_sum_re:1;
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/** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
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* a
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*/
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uint32_t tx_ack_num_re:1;
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uint32_t reserved_6:1;
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/** wait_sw_start : R/W; bitpos: [7]; default: 0;
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* a
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*/
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uint32_t wait_sw_start:1;
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/** sw_start : WT; bitpos: [8]; default: 0;
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* a
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*/
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uint32_t sw_start:1;
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uint32_t reserved_9:23;
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};
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uint32_t val;
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} uhci_conf1_reg_t;
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/** Type of escape_conf register
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* a
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*/
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typedef union {
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struct {
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/** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
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* a
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*/
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uint32_t tx_c0_esc_en:1;
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/** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
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* a
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*/
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uint32_t tx_db_esc_en:1;
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/** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
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* a
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*/
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uint32_t tx_11_esc_en:1;
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/** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
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* a
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*/
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uint32_t tx_13_esc_en:1;
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/** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
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* a
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*/
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uint32_t rx_c0_esc_en:1;
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/** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
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* a
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*/
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uint32_t rx_db_esc_en:1;
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/** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
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* a
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*/
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uint32_t rx_11_esc_en:1;
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/** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
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* a
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*/
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uint32_t rx_13_esc_en:1;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} uhci_escape_conf_reg_t;
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/** Type of hung_conf register
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* a
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*/
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typedef union {
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struct {
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/** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
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* a
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*/
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uint32_t txfifo_timeout:8;
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/** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
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* a
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*/
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uint32_t txfifo_timeout_shift:3;
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/** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
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* a
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*/
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uint32_t txfifo_timeout_ena:1;
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/** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
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* a
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*/
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uint32_t rxfifo_timeout:8;
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/** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
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* a
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*/
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uint32_t rxfifo_timeout_shift:3;
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/** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
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* a
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*/
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uint32_t rxfifo_timeout_ena:1;
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uint32_t reserved_24:8;
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};
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uint32_t val;
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} uhci_hung_conf_reg_t;
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/** Type of ack_num register
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* a
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*/
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typedef union {
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struct {
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/** ack_num : R/W; bitpos: [2:0]; default: 0;
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* a
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*/
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uint32_t ack_num:3;
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/** ack_num_load : WT; bitpos: [3]; default: 0;
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* a
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*/
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uint32_t ack_num_load:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} uhci_ack_num_reg_t;
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/** Type of quick_sent register
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* a
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*/
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typedef union {
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struct {
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/** single_send_num : R/W; bitpos: [2:0]; default: 0;
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* a
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*/
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uint32_t single_send_num:3;
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/** single_send_en : WT; bitpos: [3]; default: 0;
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* a
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*/
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uint32_t single_send_en:1;
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/** always_send_num : R/W; bitpos: [6:4]; default: 0;
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* a
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*/
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uint32_t always_send_num:3;
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/** always_send_en : R/W; bitpos: [7]; default: 0;
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* a
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*/
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uint32_t always_send_en:1;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} uhci_quick_sent_reg_t;
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/** Type of reg_qn_word0 register
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* a
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*/
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typedef union {
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struct {
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/** send_word0 : R/W; bitpos: [31:0]; default: 0;
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* a
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*/
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uint32_t send_word0:32;
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};
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uint32_t val;
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} uhci_reg_qn_word0_reg_t;
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/** Type of reg_qn_word1 register
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* a
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*/
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typedef union {
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struct {
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/** send_word1 : R/W; bitpos: [31:0]; default: 0;
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* a
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*/
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uint32_t send_word1:32;
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};
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uint32_t val;
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} uhci_reg_qn_word1_reg_t;
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/** Type of esc_conf0 register
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* a
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*/
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typedef union {
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struct {
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/** seper_char : R/W; bitpos: [7:0]; default: 192;
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* a
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*/
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uint32_t seper_char:8;
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/** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
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* a
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*/
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uint32_t seper_esc_char0:8;
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/** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
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* a
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*/
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uint32_t seper_esc_char1:8;
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uint32_t reserved_24:8;
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};
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uint32_t val;
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} uhci_esc_conf0_reg_t;
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/** Type of esc_conf1 register
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* a
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*/
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typedef union {
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struct {
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/** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
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* a
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*/
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uint32_t esc_seq0:8;
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/** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
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* a
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*/
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uint32_t esc_seq0_char0:8;
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/** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
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* a
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*/
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uint32_t esc_seq0_char1:8;
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uint32_t reserved_24:8;
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};
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uint32_t val;
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} uhci_esc_conf1_reg_t;
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/** Type of esc_conf2 register
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* a
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*/
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typedef union {
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struct {
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/** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
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* a
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*/
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uint32_t esc_seq1:8;
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/** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
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* a
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*/
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uint32_t esc_seq1_char0:8;
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/** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
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* a
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*/
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uint32_t esc_seq1_char1:8;
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uint32_t reserved_24:8;
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};
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uint32_t val;
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} uhci_esc_conf2_reg_t;
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/** Type of esc_conf3 register
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* a
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*/
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typedef union {
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struct {
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/** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
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* a
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*/
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uint32_t esc_seq2:8;
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/** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
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* a
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*/
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uint32_t esc_seq2_char0:8;
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/** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
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* a
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*/
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uint32_t esc_seq2_char1:8;
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uint32_t reserved_24:8;
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};
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uint32_t val;
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} uhci_esc_conf3_reg_t;
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/** Type of pkt_thres register
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* a
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*/
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typedef union {
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struct {
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/** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
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* a
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*/
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uint32_t pkt_thrs:13;
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uint32_t reserved_13:19;
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};
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uint32_t val;
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} uhci_pkt_thres_reg_t;
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/** Group: Interrupt Register */
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/** Type of int_raw register
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* a
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*/
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typedef union {
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struct {
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/** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
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* a
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*/
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uint32_t rx_start_int_raw:1;
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/** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
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* a
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*/
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uint32_t tx_start_int_raw:1;
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/** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
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* a
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*/
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uint32_t rx_hung_int_raw:1;
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/** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
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* a
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*/
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uint32_t tx_hung_int_raw:1;
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/** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
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* a
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*/
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uint32_t send_s_reg_q_int_raw:1;
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/** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
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* a
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*/
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uint32_t send_a_reg_q_int_raw:1;
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/** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
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* This is the interrupt raw bit. Triggered when there are some errors in EOF in the
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*/
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uint32_t out_eof_int_raw:1;
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/** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
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* Soft control int raw bit.
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*/
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uint32_t app_ctrl0_int_raw:1;
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/** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
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* Soft control int raw bit.
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*/
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uint32_t app_ctrl1_int_raw:1;
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uint32_t reserved_9:23;
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};
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uint32_t val;
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} uhci_int_raw_reg_t;
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/** Type of int_st register
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* a
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*/
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typedef union {
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struct {
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/** rx_start_int_st : RO; bitpos: [0]; default: 0;
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* a
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*/
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uint32_t rx_start_int_st:1;
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/** tx_start_int_st : RO; bitpos: [1]; default: 0;
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* a
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*/
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uint32_t tx_start_int_st:1;
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/** rx_hung_int_st : RO; bitpos: [2]; default: 0;
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* a
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*/
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uint32_t rx_hung_int_st:1;
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/** tx_hung_int_st : RO; bitpos: [3]; default: 0;
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* a
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*/
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uint32_t tx_hung_int_st:1;
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/** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
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* a
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*/
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uint32_t send_s_reg_q_int_st:1;
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/** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
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* a
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*/
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uint32_t send_a_reg_q_int_st:1;
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/** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
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* a
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*/
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uint32_t outlink_eof_err_int_st:1;
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/** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
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* a
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*/
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uint32_t app_ctrl0_int_st:1;
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/** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
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* a
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*/
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uint32_t app_ctrl1_int_st:1;
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uint32_t reserved_9:23;
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};
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uint32_t val;
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} uhci_int_st_reg_t;
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/** Type of int_ena register
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* a
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*/
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typedef union {
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struct {
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/** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
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* a
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*/
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uint32_t rx_start_int_ena:1;
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/** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
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* a
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*/
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uint32_t tx_start_int_ena:1;
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/** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
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* a
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*/
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uint32_t rx_hung_int_ena:1;
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/** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
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* a
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*/
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uint32_t tx_hung_int_ena:1;
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/** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
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* a
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*/
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uint32_t send_s_reg_q_int_ena:1;
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/** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
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* a
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*/
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uint32_t send_a_reg_q_int_ena:1;
|
|
/** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t outlink_eof_err_int_ena:1;
|
|
/** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t app_ctrl0_int_ena:1;
|
|
/** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t app_ctrl1_int_ena:1;
|
|
uint32_t reserved_9:23;
|
|
};
|
|
uint32_t val;
|
|
} uhci_int_ena_reg_t;
|
|
|
|
/** Type of int_clr register
|
|
* a
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** rx_start_int_clr : WT; bitpos: [0]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t rx_start_int_clr:1;
|
|
/** tx_start_int_clr : WT; bitpos: [1]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t tx_start_int_clr:1;
|
|
/** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t rx_hung_int_clr:1;
|
|
/** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t tx_hung_int_clr:1;
|
|
/** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t send_s_reg_q_int_clr:1;
|
|
/** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t send_a_reg_q_int_clr:1;
|
|
/** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t outlink_eof_err_int_clr:1;
|
|
/** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t app_ctrl0_int_clr:1;
|
|
/** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t app_ctrl1_int_clr:1;
|
|
uint32_t reserved_9:23;
|
|
};
|
|
uint32_t val;
|
|
} uhci_int_clr_reg_t;
|
|
|
|
|
|
/** Group: UHCI Status Register */
|
|
/** Type of state0 register
|
|
* a
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** rx_err_cause : RO; bitpos: [2:0]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t rx_err_cause:3;
|
|
/** decode_state : RO; bitpos: [5:3]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t decode_state:3;
|
|
uint32_t reserved_6:26;
|
|
};
|
|
uint32_t val;
|
|
} uhci_state0_reg_t;
|
|
|
|
/** Type of state1 register
|
|
* a
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** encode_state : RO; bitpos: [2:0]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t encode_state:3;
|
|
uint32_t reserved_3:29;
|
|
};
|
|
uint32_t val;
|
|
} uhci_state1_reg_t;
|
|
|
|
/** Type of rx_head register
|
|
* a
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** rx_head : RO; bitpos: [31:0]; default: 0;
|
|
* a
|
|
*/
|
|
uint32_t rx_head:32;
|
|
};
|
|
uint32_t val;
|
|
} uhci_rx_head_reg_t;
|
|
|
|
|
|
/** Group: Version Register */
|
|
/** Type of date register
|
|
* a
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** date : R/W; bitpos: [31:0]; default: 35655936;
|
|
* a
|
|
*/
|
|
uint32_t date:32;
|
|
};
|
|
uint32_t val;
|
|
} uhci_date_reg_t;
|
|
|
|
|
|
typedef struct uhci_dev_s {
|
|
volatile uhci_conf0_reg_t conf0;
|
|
volatile uhci_int_raw_reg_t int_raw;
|
|
volatile uhci_int_st_reg_t int_st;
|
|
volatile uhci_int_ena_reg_t int_ena;
|
|
volatile uhci_int_clr_reg_t int_clr;
|
|
volatile uhci_conf1_reg_t conf1;
|
|
volatile uhci_state0_reg_t state0;
|
|
volatile uhci_state1_reg_t state1;
|
|
volatile uhci_escape_conf_reg_t escape_conf;
|
|
volatile uhci_hung_conf_reg_t hung_conf;
|
|
volatile uhci_ack_num_reg_t ack_num;
|
|
volatile uhci_rx_head_reg_t rx_head;
|
|
volatile uhci_quick_sent_reg_t quick_sent;
|
|
volatile struct {
|
|
uhci_reg_qn_word0_reg_t word0;
|
|
uhci_reg_qn_word1_reg_t word1;
|
|
} q_data[7];
|
|
volatile uhci_esc_conf0_reg_t esc_conf0;
|
|
volatile uhci_esc_conf1_reg_t esc_conf1;
|
|
volatile uhci_esc_conf2_reg_t esc_conf2;
|
|
volatile uhci_esc_conf3_reg_t esc_conf3;
|
|
volatile uhci_pkt_thres_reg_t pkt_thres;
|
|
volatile uhci_date_reg_t date;
|
|
} uhci_dev_t;
|
|
|
|
extern uhci_dev_t UHCI0;
|
|
|
|
#ifndef __cplusplus
|
|
_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|