mirror of
https://github.com/espressif/esp-idf.git
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569 lines
17 KiB
C
569 lines
17 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: T0 Control and configuration registers */
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/** Type of txconfig register
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* Timer x configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:9;
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/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
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* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
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* clock of timer group.
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*/
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uint32_t tx_use_xtal:1;
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/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
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* When set, the alarm is enabled. This bit is automatically cleared once an
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* alarm occurs.
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*/
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uint32_t tx_alarm_en:1;
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uint32_t reserved_11:1;
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/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
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* When set, Timer x 's clock divider counter will be reset.
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*/
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uint32_t tx_divcnt_rst:1;
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/** tx_divider : R/W; bitpos: [28:13]; default: 1;
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* Timer x clock (Tx_clk) prescaler value.
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*/
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uint32_t tx_divider:16;
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/** tx_autoreload : R/W; bitpos: [29]; default: 1;
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* When set, timer x auto-reload at alarm is enabled.
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*/
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uint32_t tx_autoreload:1;
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/** tx_increase : R/W; bitpos: [30]; default: 1;
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* When set, the timer x time-base counter will increment every clock tick. When
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* cleared, the timer x time-base counter will decrement.
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*/
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uint32_t tx_increase:1;
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/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
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* When set, the timer x time-base counter is enabled.
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*/
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uint32_t tx_en:1;
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};
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uint32_t val;
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} timg_txconfig_reg_t;
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/** Type of txlo register
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* Timer x current value, low 32 bits
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*/
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typedef union {
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struct {
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/** tx_lo : RO; bitpos: [31:0]; default: 0;
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* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
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* of timer x can be read here.
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*/
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uint32_t tx_lo:32;
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};
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uint32_t val;
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} timg_txlo_reg_t;
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/** Type of txhi register
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* Timer x current value, high 22 bits
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*/
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typedef union {
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struct {
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/** tx_hi : RO; bitpos: [21:0]; default: 0;
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* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
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* of timer x can be read here.
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*/
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uint32_t tx_hi:22;
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uint32_t reserved_22:10;
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};
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uint32_t val;
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} timg_txhi_reg_t;
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/** Type of txupdate register
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* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** tx_update : R/W/SC; bitpos: [31]; default: 0;
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* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
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*/
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uint32_t tx_update:1;
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};
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uint32_t val;
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} timg_txupdate_reg_t;
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/** Type of txalarmlo register
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* Timer x alarm value, low 32 bits
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*/
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typedef union {
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struct {
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/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
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* Timer x alarm trigger time-base counter value, low 32 bits.
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*/
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uint32_t tx_alarm_lo:32;
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};
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uint32_t val;
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} timg_txalarmlo_reg_t;
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/** Type of txalarmhi register
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* Timer x alarm value, high bits
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*/
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typedef union {
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struct {
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/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
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* Timer x alarm trigger time-base counter value, high 22 bits.
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*/
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uint32_t tx_alarm_hi:22;
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uint32_t reserved_22:10;
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};
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uint32_t val;
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} timg_txalarmhi_reg_t;
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/** Type of txloadlo register
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* Timer x reload value, low 32 bits
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*/
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typedef union {
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struct {
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/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
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* Low 32 bits of the value that a reload will load onto timer x time-base
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* Counter.
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*/
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uint32_t tx_load_lo:32;
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};
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uint32_t val;
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} timg_txloadlo_reg_t;
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/** Type of txloadhi register
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* Timer x reload value, high 22 bits
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*/
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typedef union {
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struct {
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/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
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* High 22 bits of the value that a reload will load onto timer x time-base
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* counter.
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*/
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uint32_t tx_load_hi:22;
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uint32_t reserved_22:10;
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};
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uint32_t val;
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} timg_txloadhi_reg_t;
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/** Type of txload register
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* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
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*/
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typedef union {
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struct {
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/** tx_load : WT; bitpos: [31:0]; default: 0;
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*
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* Write any value to trigger a timer x time-base counter reload.
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*/
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uint32_t tx_load:32;
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};
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uint32_t val;
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} timg_txload_reg_t;
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/** Group: WDT Control and configuration registers */
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/** Type of wdtconfig0 register
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* Watchdog timer configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:12;
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/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
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* WDT reset CPU enable.
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*/
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uint32_t wdt_appcpu_reset_en:1;
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/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
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* WDT reset CPU enable.
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*/
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uint32_t wdt_procpu_reset_en:1;
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/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
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* When set, Flash boot protection is enabled.
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*/
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uint32_t wdt_flashboot_mod_en:1;
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/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
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* System reset signal length selection. 0: 100 ns, 1: 200 ns,
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* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
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*/
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uint32_t wdt_sys_reset_length:3;
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/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
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* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
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* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
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*/
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uint32_t wdt_cpu_reset_length:3;
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/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
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* choose WDT clock:0-apb_clk, 1-xtal_clk.
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*/
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uint32_t wdt_use_xtal:1;
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/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
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* update the WDT configuration registers
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*/
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uint32_t wdt_conf_update_en:1;
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/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
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* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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uint32_t wdt_stg3:2;
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/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
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* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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uint32_t wdt_stg2:2;
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/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
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* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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uint32_t wdt_stg1:2;
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/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
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* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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uint32_t wdt_stg0:2;
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/** wdt_en : R/W; bitpos: [31]; default: 0;
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* When set, MWDT is enabled.
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*/
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uint32_t wdt_en:1;
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};
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uint32_t val;
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} timg_wdtconfig0_reg_t;
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/** Type of wdtconfig1 register
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* Watchdog timer prescaler register
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*/
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typedef union {
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struct {
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/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
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* When set, WDT 's clock divider counter will be reset.
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*/
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uint32_t wdt_divcnt_rst:1;
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uint32_t reserved_1:15;
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/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
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* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
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* TIMG_WDT_CLK_PRESCALE.
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*/
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uint32_t wdt_clk_prescale:16;
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};
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uint32_t val;
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} timg_wdtconfig1_reg_t;
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/** Type of wdtconfig2 register
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* Watchdog timer stage 0 timeout value
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*/
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typedef union {
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struct {
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/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
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* Stage 0 timeout value, in MWDT clock cycles.
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*/
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uint32_t wdt_stg0_hold:32;
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};
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uint32_t val;
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} timg_wdtconfig2_reg_t;
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/** Type of wdtconfig3 register
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* Watchdog timer stage 1 timeout value
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*/
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typedef union {
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struct {
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/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
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* Stage 1 timeout value, in MWDT clock cycles.
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*/
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uint32_t wdt_stg1_hold:32;
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};
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uint32_t val;
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} timg_wdtconfig3_reg_t;
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/** Type of wdtconfig4 register
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* Watchdog timer stage 2 timeout value
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*/
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typedef union {
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struct {
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/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
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* Stage 2 timeout value, in MWDT clock cycles.
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*/
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uint32_t wdt_stg2_hold:32;
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};
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uint32_t val;
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} timg_wdtconfig4_reg_t;
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/** Type of wdtconfig5 register
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* Watchdog timer stage 3 timeout value
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*/
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typedef union {
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struct {
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/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
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* Stage 3 timeout value, in MWDT clock cycles.
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*/
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uint32_t wdt_stg3_hold:32;
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};
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uint32_t val;
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} timg_wdtconfig5_reg_t;
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/** Type of wdtfeed register
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* Write to feed the watchdog timer
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*/
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typedef union {
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struct {
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/** wdt_feed : WT; bitpos: [31:0]; default: 0;
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* Write any value to feed the MWDT. (WO)
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*/
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uint32_t wdt_feed:32;
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};
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uint32_t val;
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} timg_wdtfeed_reg_t;
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/** Type of wdtwprotect register
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* Watchdog write protect register
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*/
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typedef union {
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struct {
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/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
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* If the register contains a different value than its reset value, write
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* protection is enabled.
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*/
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uint32_t wdt_wkey:32;
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};
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uint32_t val;
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} timg_wdtwprotect_reg_t;
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/** Group: RTC CALI Control and configuration registers */
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/** Type of rtccalicfg register
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* RTC calibration configure register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:12;
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/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
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* 0: one-shot frequency calculation,1: periodic frequency calculation,
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*/
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uint32_t rtc_cali_start_cycling:1;
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/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
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* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
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*/
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uint32_t rtc_cali_clk_sel:2;
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/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
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* indicate one-shot frequency calculation is done.
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*/
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uint32_t rtc_cali_rdy:1;
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/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
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* Configure the time to calculate RTC slow clock's frequency.
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*/
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uint32_t rtc_cali_max:15;
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/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
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* Set this bit to start one-shot frequency calculation.
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*/
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uint32_t rtc_cali_start:1;
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};
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uint32_t val;
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} timg_rtccalicfg_reg_t;
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/** Type of rtccalicfg1 register
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* RTC calibration configure1 register
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*/
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typedef union {
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struct {
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/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
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* indicate periodic frequency calculation is done.
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*/
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uint32_t rtc_cali_cycling_data_vld:1;
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uint32_t reserved_1:6;
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/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
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* When one-shot or periodic frequency calculation is done, read this value to
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* calculate RTC slow clock's frequency.
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*/
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uint32_t rtc_cali_value:25;
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};
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uint32_t val;
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} timg_rtccalicfg1_reg_t;
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/** Type of rtccalicfg2 register
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* Timer group calibration register
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*/
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typedef union {
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struct {
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/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
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* RTC calibration timeout indicator
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*/
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uint32_t rtc_cali_timeout:1;
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uint32_t reserved_1:2;
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/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
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* Cycles that release calibration timeout reset
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*/
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uint32_t rtc_cali_timeout_rst_cnt:4;
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/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
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* Threshold value for the RTC calibration timer. If the calibration timer's value
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* exceeds this threshold, a timeout is triggered.
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*/
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uint32_t rtc_cali_timeout_thres:25;
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};
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uint32_t val;
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} timg_rtccalicfg2_reg_t;
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/** Group: Interrupt registers */
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/** Type of int_ena_timers register
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* Interrupt enable bits
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*/
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typedef union {
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struct {
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/** t0_int_ena : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the TIMG_T$x_INT interrupt.
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*/
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uint32_t t0_int_ena:1;
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/** wdt_int_ena : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the TIMG_WDT_INT interrupt.
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*/
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uint32_t wdt_int_ena:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} timg_int_ena_timers_reg_t;
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/** Type of int_raw_timers register
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* Raw interrupt status
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*/
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typedef union {
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struct {
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/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
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*/
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uint32_t t0_int_raw:1;
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/** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
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*/
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uint32_t wdt_int_raw:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} timg_int_raw_timers_reg_t;
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/** Type of int_st_timers register
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* Masked interrupt status
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*/
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typedef union {
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struct {
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/** t0_int_st : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
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*/
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uint32_t t0_int_st:1;
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/** wdt_int_st : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
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*/
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uint32_t wdt_int_st:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} timg_int_st_timers_reg_t;
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/** Type of int_clr_timers register
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* Interrupt clear bits
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*/
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typedef union {
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struct {
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/** t0_int_clr : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the TIMG_T$x_INT interrupt.
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*/
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uint32_t t0_int_clr:1;
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/** wdt_int_clr : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the TIMG_WDT_INT interrupt.
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*/
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uint32_t wdt_int_clr:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} timg_int_clr_timers_reg_t;
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/** Group: Version register */
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/** Type of ntimers_date register
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* Timer version control register
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*/
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typedef union {
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struct {
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/** ntimgs_date : R/W; bitpos: [27:0]; default: 35676274;
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* Timer version control register
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|
*/
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uint32_t ntimgs_date:28;
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|
uint32_t reserved_28:4;
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|
};
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|
uint32_t val;
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|
} timg_ntimers_date_reg_t;
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|
|
|
|
|
/** Group: Clock configuration registers */
|
|
/** Type of regclk register
|
|
* Timer group clock gate register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
uint32_t reserved_0:28;
|
|
/** etm_en : R/W; bitpos: [28]; default: 1;
|
|
* enable timer's etm task and event
|
|
*/
|
|
uint32_t etm_en:1;
|
|
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
|
|
* enable WDT's clock
|
|
*/
|
|
uint32_t wdt_clk_is_active:1;
|
|
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
|
|
* enable Timer $x's clock
|
|
*/
|
|
uint32_t timer_clk_is_active:1;
|
|
/** clk_en : R/W; bitpos: [31]; default: 0;
|
|
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
|
* Registers can not be read or written to by software.
|
|
*/
|
|
uint32_t clk_en:1;
|
|
};
|
|
uint32_t val;
|
|
} timg_regclk_reg_t;
|
|
|
|
|
|
typedef struct {
|
|
volatile timg_txconfig_reg_t config;
|
|
volatile timg_txlo_reg_t lo;
|
|
volatile timg_txhi_reg_t hi;
|
|
volatile timg_txupdate_reg_t update;
|
|
volatile timg_txalarmlo_reg_t alarmlo;
|
|
volatile timg_txalarmhi_reg_t alarmhi;
|
|
volatile timg_txloadlo_reg_t loadlo;
|
|
volatile timg_txloadhi_reg_t loadhi;
|
|
volatile timg_txload_reg_t load;
|
|
} timg_hwtimer_reg_t;
|
|
|
|
|
|
typedef struct timg_dev_t {
|
|
volatile timg_hwtimer_reg_t hw_timer[1];
|
|
uint32_t reserved_024[9];
|
|
volatile timg_wdtconfig0_reg_t wdtconfig0;
|
|
volatile timg_wdtconfig1_reg_t wdtconfig1;
|
|
volatile timg_wdtconfig2_reg_t wdtconfig2;
|
|
volatile timg_wdtconfig3_reg_t wdtconfig3;
|
|
volatile timg_wdtconfig4_reg_t wdtconfig4;
|
|
volatile timg_wdtconfig5_reg_t wdtconfig5;
|
|
volatile timg_wdtfeed_reg_t wdtfeed;
|
|
volatile timg_wdtwprotect_reg_t wdtwprotect;
|
|
volatile timg_rtccalicfg_reg_t rtccalicfg;
|
|
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
|
|
volatile timg_int_ena_timers_reg_t int_ena_timers;
|
|
volatile timg_int_raw_timers_reg_t int_raw_timers;
|
|
volatile timg_int_st_timers_reg_t int_st_timers;
|
|
volatile timg_int_clr_timers_reg_t int_clr_timers;
|
|
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
|
|
uint32_t reserved_084[29];
|
|
volatile timg_ntimers_date_reg_t ntimers_date;
|
|
volatile timg_regclk_reg_t regclk;
|
|
} timg_dev_t;
|
|
|
|
extern timg_dev_t TIMERG0;
|
|
extern timg_dev_t TIMERG1;
|
|
|
|
#ifndef __cplusplus
|
|
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|