mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
200 lines
8.7 KiB
ArmAsm
200 lines
8.7 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "portmacro.h"
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#include "freertos/FreeRTOSConfig.h"
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#include "soc/soc_caps.h"
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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#include "esp_private/hw_stack_guard.h"
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#endif
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.global port_uxInterruptNesting
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.global port_xSchedulerRunning
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.global xIsrStackTop
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.global pxCurrentTCB
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.global vTaskSwitchContext
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.global xPortSwitchFlag
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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.global xIsrStackBottom
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.global port_offset_pxStack
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.global port_offset_pxEndOfStack
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.global esp_hw_stack_guard_monitor_stop
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.global esp_hw_stack_guard_monitor_start
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.global esp_hw_stack_guard_set_bounds
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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.section .text
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/**
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* This function makes the RTOS aware about an ISR entering. It takes the
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* current task stack pointer and places it into the pxCurrentTCB.
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* It then loads the ISR stack into sp.
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* TODO: ISR nesting code improvements ?
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* In the routines below, let's use a0-a5 registers to let the compiler generate
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* 16-bit instructions.
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*/
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.global rtos_int_enter
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.type rtos_int_enter, @function
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rtos_int_enter:
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#if ( configNUM_CORES > 1 )
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csrr a5, mhartid /* a5 = coreID */
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slli a5, a5, 2 /* a5 = coreID * 4 */
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la a0, port_xSchedulerRunning /* a0 = &port_xSchedulerRunning */
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add a0, a0, a5 /* a0 = &port_xSchedulerRunning[coreID] */
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lw a0, (a0) /* a0 = port_xSchedulerRunning[coreID] */
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#else
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lw a0, port_xSchedulerRunning /* a0 = port_xSchedulerRunning */
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#endif /* ( configNUM_CORES > 1 ) */
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beqz a0, rtos_int_enter_end /* if (port_xSchedulerRunning[coreID] == 0) jump to rtos_int_enter_end */
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/* Increment the ISR nesting count */
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la a0, port_uxInterruptNesting /* a0 = &port_uxInterruptNesting */
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#if ( configNUM_CORES > 1 )
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add a0, a0, a5 /* a0 = &port_uxInterruptNesting[coreID] // a5 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw a1, 0(a0) /* a1 = port_uxInterruptNesting[coreID] */
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addi a2, a1, 1 /* a2 = a1 + 1 */
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sw a2, 0(a0) /* port_uxInterruptNesting[coreID] = a2 */
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/* If we reached here from another low-priority ISR, i.e, port_uxInterruptNesting[coreID] > 0, then skip stack pushing to TCB */
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bnez a1, rtos_int_enter_end /* if (port_uxInterruptNesting[coreID] > 0) jump to rtos_int_enter_end */
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_monitor_stop(); pass the scratch registers */
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ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE a0 a1
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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/* Save the current sp in pxCurrentTCB[coreID] and load the ISR stack on to sp */
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#if ( configNUM_CORES > 1 )
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la a0, pxCurrentTCB /* a0 = &pxCurrentTCB */
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add a0, a0, a5 /* a0 = &pxCurrentTCB[coreID] // a5 already contains coreID * 4 */
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lw a0, (a0) /* a0 = pxCurrentTCB[coreID] */
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sw sp, 0(a0) /* pxCurrentTCB[coreID] = sp */
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la a0, xIsrStackTop /* a0 = &xIsrStackTop */
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add a0, a0, a5 /* a0 = &xIsrStackTop[coreID] // a5 already contains coreID * 4 */
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lw sp, (a0) /* sp = xIsrStackTop[coreID] */
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#else
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lw a0, pxCurrentTCB /* a0 = pxCurrentTCB */
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sw sp, 0(a0) /* pxCurrentTCB[0] = sp */
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lw sp, xIsrStackTop /* sp = xIsrStackTop */
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#endif /* ( configNUM_CORES > 1 ) */
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* Prepare the parameters for esp_hw_stack_guard_set_bounds(xIsrStackBottom, xIsrStackTop); */
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#if ( configNUM_CORES > 1 )
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/* Load the xIsrStack for the current core and set the new bounds */
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la a0, xIsrStackBottom
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add a0, a0, a5 /* a0 = &xIsrStackBottom[coreID] */
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lw a0, (a0) /* a0 = xIsrStackBottom[coreID] */
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#else
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lw a0, xIsrStackBottom
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#endif /* ( configNUM_CORES > 1 ) */
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mv a1, sp
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/* esp_hw_stack_guard_set_bounds(xIsrStackBottom[coreID], xIsrStackTop[coreID]);
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*/
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ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE a2
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ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE a0 a1
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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rtos_int_enter_end:
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ret
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/**
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* Restore the stack pointer of the next task to run.
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*/
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.global rtos_int_exit
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.type rtos_int_exit, @function
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rtos_int_exit:
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#if ( configNUM_CORES > 1 )
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csrr a1, mhartid /* a1 = coreID */
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slli a1, a1, 2 /* a1 = a1 * 4 */
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la a0, port_xSchedulerRunning /* a0 = &port_xSchedulerRunning */
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add a0, a0, a1 /* a0 = &port_xSchedulerRunning[coreID] */
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lw a0, (a0) /* a0 = port_xSchedulerRunning[coreID] */
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#else
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lw a0, port_xSchedulerRunning /* a0 = port_xSchedulerRunning */
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#endif /* ( configNUM_CORES > 1 ) */
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beqz a0, rtos_int_exit_end /* if (port_uxSchewdulerRunning == 0) jump to rtos_int_exit_end */
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/* Update nesting interrupts counter */
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la a0, port_uxInterruptNesting /* a0 = &port_uxInterruptNesting */
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#if ( configNUM_CORES > 1 )
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add a0, a0, a1 /* a0 = &port_uxInterruptNesting[coreID] // a1 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw a2, 0(a0) /* a2 = port_uxInterruptNesting[coreID] */
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/* Already zero, protect against underflow */
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beqz a2, isr_skip_decrement /* if (port_uxInterruptNesting[coreID] == 0) jump to isr_skip_decrement */
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addi a2, a2, -1 /* a2 = a2 - 1 */
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sw a2, 0(a0) /* port_uxInterruptNesting[coreID] = a2 */
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/* May still have interrupts pending, skip section below and exit */
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bnez a2, rtos_int_exit_end
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isr_skip_decrement:
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/* If the CPU reached this label, a2 (uxInterruptNesting) is 0 for sure */
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/* Schedule the next task if a yield is pending */
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la a0, xPortSwitchFlag /* a0 = &xPortSwitchFlag */
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#if ( configNUM_CORES > 1 )
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add a0, a0, a1 /* a0 = &xPortSwitchFlag[coreID] // a1 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw a2, 0(a0) /* a2 = xPortSwitchFlag[coreID] */
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beqz a2, no_switch /* if (xPortSwitchFlag[coreID] == 0) jump to no_switch */
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/* Preserve return address and schedule next task. To speed up the process, instead of allocating stack
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* space, let's use a callee-saved register: s0. Since the caller is not using it, let's use it. */
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mv s0, ra
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call vTaskSwitchContext
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mv ra, s0
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/* Clears the switch pending flag */
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la a0, xPortSwitchFlag /* a0 = &xPortSwitchFlag */
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#if ( configNUM_CORES > 1 )
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/* C routine vTaskSwitchContext may change the temp registers, so we read again */
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csrr a1, mhartid /* a1 = coreID */
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slli a1, a1, 2 /* a1 = a1 * 4 */
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add a0, a0, a1 /* a0 = &xPortSwitchFlag[coreID]; */
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#endif /* ( configNUM_CORES > 1 ) */
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sw zero, 0(a0) /* xPortSwitchFlag[coreID] = 0; */
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no_switch:
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_monitor_stop(); pass the scratch registers */
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ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE a0 a1
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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#if ( configNUM_CORES > 1 )
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/* Recover the stack of next task and prepare to exit */
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csrr a1, mhartid
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slli a1, a1, 2
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la a0, pxCurrentTCB /* a0 = &pxCurrentTCB */
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add a0, a0, a1 /* a0 = &pxCurrentTCB[coreID] */
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lw a0, 0(a0) /* a0 = pxCurrentTCB[coreID] */
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lw sp, 0(a0) /* sp = previous sp */
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#else
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/* Recover the stack of next task */
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lw a0, pxCurrentTCB
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lw sp, 0(a0)
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#endif /* ( configNUM_CORES > 1 ) */
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_set_bounds(pxCurrentTCB[0]->pxStack,
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* pxCurrentTCB[0]->pxEndOfStack);
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*/
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lw a1, PORT_OFFSET_PX_END_OF_STACK(a0)
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lw a0, PORT_OFFSET_PX_STACK(a0)
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ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE a2
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/* esp_hw_stack_guard_monitor_start(); */
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ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE a0 a1
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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rtos_int_exit_end:
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ret
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