Omar Chebib e1d3993309 RISC-V: Fix vectors.S assembly file indentation and macro usage ... The file is now more consistent as the macros have been fixed, more comments have been added and the indentation is now using spaces only.		2022-04-22 13:17:59 +03:00
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include	riscv: Use semihosting to set breakpoint and watchpoint when running under debugger	2022-04-22 13:17:54 +03:00
CMakeLists.txt	arch: move stdatomic	2021-11-02 16:24:18 +01:00
expression_with_stack_riscv_asm.S	core: fix cases where riscv SP were not 16 byte aligned	2021-06-02 16:02:10 +08:00
expression_with_stack_riscv.c	core: fix cases where riscv SP were not 16 byte aligned	2021-06-02 16:02:10 +08:00
instruction_decode.c	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
interrupt.c	interrupt: removed descriptor table from esp32c3 interrupt hal.	2021-01-05 15:39:46 +08:00
linker.lf	arch: move stdatomic	2021-11-02 16:24:18 +01:00
stdatomic.c	stdatomic: Implemented legacy __sync APIs and __atomic_exchange_n	2021-04-27 13:34:54 +05:30
vectors.S	RISC-V: Fix vectors.S assembly file indentation and macro usage	2022-04-22 13:17:59 +03:00