mirror of
https://github.com/espressif/esp-idf.git
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71 lines
2.6 KiB
C
71 lines
2.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "hal/efuse_hal.h"
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#include "soc/rtc_cntl_reg.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "hal/clk_tree_ll.h"
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#endif
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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__attribute__((weak)) void bootloader_clock_configure(void)
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{
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// ROM bootloader may have put a lot of text into UART0 FIFO.
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// Wait for it to be printed.
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// This is not needed on power on reset, when ROM bootloader is running at
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// 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
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// and will be done with the bootloader much earlier than UART FIFO is empty.
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esp_rom_uart_tx_wait_idle(0);
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/* Set CPU to 80MHz. Keep other clocks unmodified. */
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int cpu_freq_mhz = 80;
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#if CONFIG_IDF_TARGET_ESP32
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/* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
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* 240 MHz may cause the chip to lock up (see section 3.5 of the errata
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* document). For rev. 0, switch to 240 instead if it has been enabled
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* previously.
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*/
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if (efuse_hal_get_major_chip_version() == 0 &&
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clk_ll_cpu_get_freq_mhz_from_pll() == CLK_LL_PLL_240M_FREQ_MHZ) {
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cpu_freq_mhz = 240;
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}
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#elif CONFIG_IDF_TARGET_ESP32H2
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cpu_freq_mhz = 64;
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#endif
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if (esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW || rtc_clk_apb_freq_get() < APB_CLK_FREQ) {
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rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
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clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
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clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
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if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
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clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
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}
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clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
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if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
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clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
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}
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rtc_clk_init(clk_cfg);
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}
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/* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
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* it here. Usually it needs some time to start up, so we amortize at least
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* part of the start up time by enabling 32k XTAL early.
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* App startup code will wait until the oscillator has started up.
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*/
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#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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if (!rtc_clk_32k_enabled()) {
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rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
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}
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#endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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}
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