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https://github.com/espressif/esp-idf.git
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182e937c5a
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/**
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* @file regi2c_dig_reg.h
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* @brief Register definitions for digital to get rtc voltage & digital voltage
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* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
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*/
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#define I2C_DIG_REG 0x6D
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#define I2C_DIG_REG_HOSTID 0
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#define I2C_DIG_REG_EXT_RTC_DREG 4
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#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
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#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
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#define I2C_DIG_REG_ENX_RTC_DREG 4
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#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
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#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
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#define I2C_DIG_REG_ENIF_RTC_DREG 5
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#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7
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#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7
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#define I2C_DIG_REG_EXT_DIG_DREG 6
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#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
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#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
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#define I2C_DIG_REG_ENX_DIG_DREG 6
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#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7
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#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
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#define I2C_DIG_REG_ENIF_DIG_DREG 7
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#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7
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#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7
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#define I2C_DIG_REG_OR_EN_CONT_CAL 9
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#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
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#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
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#define I2C_DIG_REG_XPD_RTC_REG 13
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#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
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#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
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#define I2C_DIG_REG_XPD_DIG_REG 13
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#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
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#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
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#define I2C_DIG_REG_SCK_DCAP 14
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#define I2C_DIG_REG_SCK_DCAP_MSB 7
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#define I2C_DIG_REG_SCK_DCAP_LSB 0
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