mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-20 10:46:02 -04:00
42dfb5cadd
After this commit, when physical address is larger than vaddr range, driver will still map as much as it can, but also give a verbose level log to show the actual mapped size
347 lines
12 KiB
C
347 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*----------------------------------------------------------------------------------------------------
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* Abstraction layer for PSRAM. PSRAM device related registers and MMU/Cache related code shouls be
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* abstracted to lower layers.
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*
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* When we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
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*----------------------------------------------------------------------------------------------------*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "esp_heap_caps_init.h"
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#include "hal/mmu_hal.h"
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#include "hal/cache_ll.h"
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#include "esp_private/esp_psram_io.h"
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#include "esp_private/esp_psram_extram.h"
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#include "esp_private/mmu.h"
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#include "esp_psram_impl.h"
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#include "esp_psram.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/himem.h"
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#include "esp32/rom/cache.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_FREERTOS_UNICORE
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#else
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#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
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#endif
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#else
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#endif
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#if CONFIG_SPIRAM
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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extern uint8_t _ext_ram_bss_start;
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extern uint8_t _ext_ram_bss_end;
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#endif //#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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extern uint8_t _ext_ram_noinit_start;
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extern uint8_t _ext_ram_noinit_end;
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#endif //#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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//These variables are in bytes
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static intptr_t s_allocable_vaddr_start;
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static intptr_t s_allocable_vaddr_end;
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static intptr_t s_mapped_vaddr_start;
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static intptr_t s_mapped_vaddr_end;
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static bool s_spiram_inited;
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static const char* TAG = "esp_psram";
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#if CONFIG_IDF_TARGET_ESP32
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//If no function in esp_himem.c is used, this function will be linked into the
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//binary instead of the one in esp_himem.c, automatically making sure no memory
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//is reserved if no himem function is used.
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size_t __attribute__((weak)) esp_himem_reserved_area_size(void) {
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return 0;
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}
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static void IRAM_ATTR s_mapping(int v_start, int size)
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{
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//Enable external RAM in MMU
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cache_sram_mmu_set(0, 0, v_start, 0, 32, (size / 1024 / 32));
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//Flush and enable icache for APP CPU
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#if !CONFIG_FREERTOS_UNICORE
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
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cache_sram_mmu_set(1, 0, v_start, 0, 32, (size / 1024 / 32));
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#endif
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}
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#endif //CONFIG_IDF_TARGET_ESP32
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esp_err_t esp_psram_init(void)
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{
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if (s_spiram_inited) {
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return ESP_ERR_INVALID_STATE;
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}
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esp_err_t ret;
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ret = esp_psram_impl_enable(PSRAM_MODE);
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if (ret != ESP_OK) {
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#if CONFIG_SPIRAM_IGNORE_NOTFOUND
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ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out.");
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#endif
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return ret;
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}
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s_spiram_inited = true;
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uint32_t psram_physical_size = 0;
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ret = esp_psram_impl_get_physical_size(&psram_physical_size);
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assert(ret == ESP_OK);
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ESP_EARLY_LOGI(TAG, "Found %dMB SPI RAM device", psram_physical_size / (1024 * 1024));
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ESP_EARLY_LOGI(TAG, "Speed: %dMHz", CONFIG_SPIRAM_SPEED);
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#if CONFIG_IDF_TARGET_ESP32
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ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
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(PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \
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(PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \
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(PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR");
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#endif
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uint32_t psram_available_size = 0;
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ret = esp_psram_impl_get_available_size(&psram_available_size);
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assert(ret == ESP_OK);
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__attribute__((unused)) uint32_t total_available_size = psram_available_size;
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/**
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* `start_page` is the psram physical address in MMU page size.
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* MMU page size on ESP32S2 is 64KB
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* e.g.: psram physical address 16 is in page 0
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*
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* Here we plan to copy FLASH instructions to psram physical address 0, which is the No.0 page.
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*/
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__attribute__((unused)) uint32_t start_page = 0;
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
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uint32_t used_page = 0;
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#endif
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//------------------------------------Copy Flash .text to PSRAM-------------------------------------//
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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ret = mmu_config_psram_text_segment(start_page, total_available_size, &used_page);
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if (ret != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "No enough psram memory for instructon!");
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abort();
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}
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start_page += used_page;
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psram_available_size -= MMU_PAGE_TO_BYTES(used_page);
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ESP_EARLY_LOGV(TAG, "after copy .text, used page is %d, start_page is %d, psram_available_size is %d B", used_page, start_page, psram_available_size);
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#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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//------------------------------------Copy Flash .rodata to PSRAM-------------------------------------//
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#if CONFIG_SPIRAM_RODATA
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ret = mmu_config_psram_rodata_segment(start_page, total_available_size, &used_page);
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if (ret != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "No enough psram memory for rodata!");
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abort();
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}
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start_page += used_page;
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psram_available_size -= MMU_PAGE_TO_BYTES(used_page);
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ESP_EARLY_LOGV(TAG, "after copy .rodata, used page is %d, start_page is %d, psram_available_size is %d B", used_page, start_page, psram_available_size);
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#endif //#if CONFIG_SPIRAM_RODATA
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//----------------------------------Map the PSRAM physical range to MMU-----------------------------//
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intptr_t vaddr_start = mmu_get_psram_vaddr_start();
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if (vaddr_start + psram_available_size > mmu_get_psram_vaddr_end()) {
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psram_available_size = mmu_get_psram_vaddr_end() - vaddr_start;
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ESP_EARLY_LOGV(TAG, "Virtual address not enough for PSRAM, map as much as we can. %dMB is mapped", psram_available_size / 1024 / 1024);
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}
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#if CONFIG_IDF_TARGET_ESP32
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s_mapping(vaddr_start, psram_available_size);
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#else
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uint32_t actual_mapped_len = 0;
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mmu_hal_map_region(0, MMU_TARGET_PSRAM0, vaddr_start, MMU_PAGE_TO_BYTES(start_page), psram_available_size, &actual_mapped_len);
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ESP_EARLY_LOGV(TAG, "actual_mapped_len is 0x%x bytes", actual_mapped_len);
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, vaddr_start, actual_mapped_len);
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cache_ll_l1_enable_bus(0, bus_mask);
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#if !CONFIG_FREERTOS_UNICORE
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bus_mask = cache_ll_l1_get_bus(1, vaddr_start, actual_mapped_len);
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cache_ll_l1_enable_bus(1, bus_mask);
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#endif
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#endif //#if CONFIG_IDF_TARGET_ESP32
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/*------------------------------------------------------------------------------
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* After mapping, we DON'T care about the PSRAM PHYSICAL ADDRESSS ANYMORE!
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*----------------------------------------------------------------------------*/
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s_mapped_vaddr_start = vaddr_start;
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s_mapped_vaddr_end = vaddr_start + psram_available_size;
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s_allocable_vaddr_start = vaddr_start;
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s_allocable_vaddr_end = vaddr_start + psram_available_size;
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//------------------------------------Configure .bss in PSRAM-------------------------------------//
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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//should never be negative number
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uint32_t ext_bss_size = ((intptr_t)&_ext_ram_bss_end - (intptr_t)&_ext_ram_bss_start);
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ESP_EARLY_LOGV(TAG, "ext_bss_size is %d", ext_bss_size);
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s_allocable_vaddr_start += ext_bss_size;
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#endif //#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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uint32_t ext_noinit_size = ((intptr_t)&_ext_ram_noinit_end - (intptr_t)&_ext_ram_noinit_start);
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ESP_EARLY_LOGV(TAG, "ext_noinit_size is %d", ext_noinit_size);
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s_allocable_vaddr_start += ext_noinit_size;
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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s_allocable_vaddr_end -= esp_himem_reserved_area_size() - 1;
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#endif
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ESP_EARLY_LOGV(TAG, "s_allocable_vaddr_start is 0x%x, s_allocable_vaddr_end is 0x%x", s_allocable_vaddr_start, s_allocable_vaddr_end);
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return ESP_OK;
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}
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/**
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* Add the PSRAM available region to heap allocator. Heap allocator knows the capabilities of this type of memory,
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* so there's no need to explicitly specify them.
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*/
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esp_err_t esp_psram_extram_add_to_heap_allocator(void)
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{
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ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (s_allocable_vaddr_end - s_allocable_vaddr_start) / 1024);
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return heap_caps_add_region(s_allocable_vaddr_start, s_allocable_vaddr_end);
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}
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esp_err_t IRAM_ATTR esp_psram_extram_get_mapped_range(intptr_t *out_vstart, intptr_t *out_vend)
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{
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if (!out_vstart || !out_vend) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!s_spiram_inited) {
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return ESP_ERR_INVALID_STATE;
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}
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*out_vstart = s_mapped_vaddr_start;
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*out_vend = s_mapped_vaddr_end;
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return ESP_OK;
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}
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esp_err_t esp_psram_extram_get_alloced_range(intptr_t *out_vstart, intptr_t *out_vend)
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{
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if (!out_vstart || !out_vend) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!s_spiram_inited) {
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return ESP_ERR_INVALID_STATE;
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}
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*out_vstart = s_allocable_vaddr_start;
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*out_vend = s_allocable_vaddr_end;
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return ESP_OK;
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}
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esp_err_t esp_psram_extram_reserve_dma_pool(size_t size)
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{
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if (size == 0) {
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return ESP_OK; //no-op
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}
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ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size / 1024);
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/* Pool may be allocated in multiple non-contiguous chunks, depending on available RAM */
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while (size > 0) {
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size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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next_size = MIN(next_size, size);
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ESP_EARLY_LOGD(TAG, "Allocating block of size %d bytes", next_size);
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uint8_t *dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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if (!dma_heap || next_size == 0) {
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return ESP_ERR_NO_MEM;
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}
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uint32_t caps[] = {0, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT};
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esp_err_t e = heap_caps_add_region_with_caps(caps, (intptr_t)dma_heap, (intptr_t)dma_heap + next_size - 1);
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if (e != ESP_OK) {
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return e;
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}
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size -= next_size;
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}
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return ESP_OK;
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}
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bool IRAM_ATTR esp_psram_is_initialized(void)
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{
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return s_spiram_inited;
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}
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size_t esp_psram_get_size(void)
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{
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uint32_t available_size = 0;
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esp_err_t ret = esp_psram_impl_get_available_size(&available_size);
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if (ret != ESP_OK) {
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//This means PSRAM isn't initialised, to keep back-compatibility, set size to 0.
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available_size = 0;
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}
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return (size_t)available_size;
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}
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uint8_t esp_psram_io_get_cs_io(void)
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{
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return esp_psram_impl_get_cs_io();
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}
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/*
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Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
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true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
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initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
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*/
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bool esp_psram_extram_test(void)
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{
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#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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const void *keepout_addr_low = (const void*)&_ext_ram_noinit_start;
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const void *keepout_addr_high = (const void*)&_ext_ram_noinit_end;
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#else
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const void *keepout_addr_low = 0;
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const void *keepout_addr_high = 0;
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#endif
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volatile int *spiram = (volatile int *)s_mapped_vaddr_start;
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size_t p;
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size_t s = s_mapped_vaddr_end - s_mapped_vaddr_start;
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int errct=0;
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int initial_err=-1;
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for (p=0; p<(s/sizeof(int)); p+=8) {
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const void *addr = (const void *)&spiram[p];
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if ((keepout_addr_low <= addr) && (addr < keepout_addr_high)) {
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continue;
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}
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spiram[p]=p^0xAAAAAAAA;
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}
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for (p=0; p<(s/sizeof(int)); p+=8) {
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const void *addr = (const void *)&spiram[p];
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if ((keepout_addr_low <= addr) && (addr < keepout_addr_high)) {
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continue;
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}
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if (spiram[p]!=(p^0xAAAAAAAA)) {
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errct++;
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if (errct==1) initial_err=p*4;
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}
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}
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if (errct) {
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ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err + s_mapped_vaddr_start);
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return false;
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} else {
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ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
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return true;
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}
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}
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#endif //#if CONFIG_SPIRAM
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