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302 lines
8.7 KiB
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302 lines
8.7 KiB
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***********************
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Chip Series Comparison
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***********************
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:link_to_translation:`zh_CN:[中文]`
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The comparison below covers key features of chips supported by ESP-IDF. For the full list of features please refer to respective datasheets in Section `Related Documents`_.
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.. list-table:: Chip Series Comparison
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:widths: 20 40 40 40 40
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:header-rows: 1
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* - Feature
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- ESP32 Series
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- ESP32-S2 Series
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- ESP32-C3 Series
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- ESP32-S3 Series
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* - Launch year
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- 2016
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- 2020
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- 2020
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- 2020
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* - Variants
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- See `ESP32 Datasheet (PDF) <https://espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_
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- See `ESP32-S2 Datasheet (PDF) <https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf>`_
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- See `ESP32-C3 Datasheet (PDF) <https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf>`_
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- See `ESP32-S3 Datasheet (PDF) <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_
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* - Core
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- Xtensa® dual-/single core 32-bit LX6
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- Xtensa® single-core 32-bit LX7
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- 32-bit single-core RISC-V
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- Xtensa® dual-core 32-bit LX7
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* - Wi-Fi protocols
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- 802.11 b/g/n, 2.4 GHz
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- 802.11 b/g/n, 2.4 GHz
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- 802.11 b/g/n, 2.4 GHz
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- 802.11 b/g/n, 2.4 GHz
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* - Bluetooth®
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- Bluetooth v4.2 BR/EDR and Bluetooth Low Energy
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- ✖️
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- Bluetooth 5.0
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- Bluetooth 5.0
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* - Typical frequency
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- 240 MHz (160 MHz for ESP32-S0WD)
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- 240 MHz
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- 160 MHz
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- 240 MHz
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* - SRAM
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- 520 KB
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- 320 KB
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- 400 KB
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- 512 KB
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* - ROM
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- 448 KB for booting and core functions
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- 128 KB for booting and core functions
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- 384 KB for booting and core functions
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- 384 KB for booting and core functions
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* - Embedded flash
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- 2 MB, 4 MB, or none, depending on variants
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- 2 MB, 4 MB, or none, depending on variants
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- 4 MB or none, depending on variants
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- 8 MB or none, depending on variants
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* - External flash
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- Up to 16 MB device, address 11 MB + 248 KB each time
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- Up to 1 GB device, address 11.5 MB each time
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- Up to 16 MB device, address 8 MB each time
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- Up to 1 GB device, address 32 MB each time
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* - External RAM
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- Up to 8 MB device, address 4 MB each time
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- Up to 1 GB device, address 11.5 MB each time
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- ✖️
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- Up to 1 GB device, address 32 MB each time
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* - Cache
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- ✔️ Two-way set associative
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- ✔️ Four-way set associative, independent instruction cache and data cache
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- ✔️ Eight-way set associative, 32-bit data/instruction bus width
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- ✔️ Four-way or eight-way set associative for instruction cache; four-way set associative for data cache, 32-bit data/instruction bus width
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* - **Peripherals**
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-
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-
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* - ADC
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- Two 12-bit, 18 channels
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- Two 12-bit, 20 channels
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- Two 12-bit SAR ADCs, at most 6 channels
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- Two 12-bit SAR ADCs, 20 channels
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* - DAC
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- Two 8-bit channels
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- Two 8-bit channels
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- ✖️
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- ✖️
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* - Timers
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- Four 64-bit general-purpose timers, and three watchdog timers
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- Four 64-bit general-purpose timers, and three watchdog timers
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- Two 54-bit general-purpose timers, and three watchdog timers
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- Four 54-bit general-purpose timers, and three watchdog timers
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* - Temperature sensor
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- ✖️
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- 1
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- 1
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- 1
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* - Touch sensor
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- 10
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- 14
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- ✖️
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- 14
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* - Hall sensor
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- 1
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- ✖️
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- ✖️
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- ✖️
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* - GPIO
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- 34
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- 43
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- 22
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- 45
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* - SPI
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- 4
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- 4
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- 3
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- 4
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* - LCD interface
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- 1
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- 1
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- ✖️
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- 1
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* - UART
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- 3
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- 2 :sup:`1`
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- 2 :sup:`1`
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- 3
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* - I2C
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- 2
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- 2
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- 1
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- 2
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* - I2S
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- 2, can be configured to operate with 8/16/32/40/48-bit resolution as an input or output channel.
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- 1, can be configured to operate with 8/16/24/32/48/64-bit resolution as an input or output channel.
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- 1, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel.
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- 2, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel.
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* - Camera interface
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- 1
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- 1
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- ✖️
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- 1
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* - DMA
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- Dedicated DMA to UART, SPI, I2S, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi
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- Dedicated DMA to UART, SPI, AES, SHA, I2S, and ADC Controller
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- General-purpose, 3 TX channels, 3 RX channels
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- General-purpose, 5 TX channels, 5 RX channels
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* - RMT
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- 8 channels
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- 4 channels :sup:`1`, can be configured to TX/RX channels
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- 4 channels :sup:`2`, 2 TX channels, 2 RX channels
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- 8 channels :sup:`2`, 4 TX channels, 4 RX channels
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* - Pulse counter
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- 8 channels
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- 4 channels :sup:`1`
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- ✖️
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- 4 channels :sup:`1`
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* - LED PWM
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- 16 channels
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- 8 channels :sup:`1`
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- 6 channels :sup:`2`
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- 8 channels :sup:`1`
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* - MCPWM
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- 2, six PWM outputs
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- ✖️
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- ✖️
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- 2, six PWM outputs
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* - USB OTG
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- ✖️
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- 1
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- ✖️
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- 1
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* - TWAI® controller (compatible with ISO 11898-1)
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- 1
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- 1
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- 1
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- 1
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* - SD/SDIO/MMC host controller
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- 1
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- ✖️
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- ✖️
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- 1
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* - SDIO slave controller
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- 1
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- ✖️
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- ✖️
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- ✖️
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* - Ethernet MAC
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- 1
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- ✖️
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- ✖️
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- ✖️
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* - ULP
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- ULP FSM
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- PicoRV32 core with 8 KB SRAM, ULP FSM
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- ✖️
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- PicoRV32 core with 8 KB SRAM, ULP FSM
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* - Debug Assist
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- ✖️
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- ✖️
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- 1
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- ✖️
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* - **Security**
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-
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* - Secure boot
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- ✔️
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- ✔️ Faster and safer, compared with ESP32
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- ✔️ Faster and safer, compared with ESP32
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- ✔️ Faster and safer, compared with ESP32
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* - Flash encryption
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- ✔️
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- ✔️ Support for PSRAM encryption. Safer, compared with ESP32
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- ✔️ Safer, compared with ESP32
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- ✔️ Support for PSRAM encryption. Safer, compared with ESP32
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* - OTP
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- 1024-bit
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- 4096-bit
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- 4096-bit
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- 4096-bit
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* - AES
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- ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197)
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- ✔️ AES-128, AES-192, AES-256 (FIPS PUB 197); DMA support
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- ✔️ AES-128, AES-256 (FIPS PUB 197); DMA support
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- ✔️ AES-128, AES-256 (FIPS PUB 197); DMA support
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* - HASH
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- SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4)
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- SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support
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- SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4); DMA support
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- SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support
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* - RSA
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- Up to 4096 bits
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- Up to 4096 bits
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- Up to 3072 bits
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- Up to 4096 bits
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* - RNG
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- ✔️
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- ✔️
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- ✔️
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- ✔️
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* - HMAC
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- ✖️
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- ✔️
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- ✔️
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- ✔️
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* - Digital signature
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- ✖️
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- ✔️
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- ✔️
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- ✔️
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* - XTS
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- ✖️
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- ✔️ XTS-AES-128, XTS-AES-256
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- ✔️ XTS-AES-128
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- ✔️ XTS-AES-128, XTS-AES-256
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* - **Other**
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-
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-
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* - Deep-sleep (ULP sensor-monitored pattern)
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- 100 μA (when ADC work with a duty cycle of 1%)
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- 22 μA (when touch sensors work with a duty cycle of 1%)
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- No such pattern
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- TBD
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* - Size
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- QFN48 5*5, 6*6, depending on variants
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- QFN56 7*7
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- QFN32 5*5
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- QFN56 7*7
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- **Note** 1: Reduced chip area compared with ESP32
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- **Note** 2: Reduced chip area compared with ESP32 and ESP32-S2
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- **Note** 3: Die size: ESP32-C3 < ESP32-S2 < ESP32-S3 < ESP32
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Related Documents
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=================
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- `ESP32 Datasheet (PDF) <https://espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_
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- ESP32-PICO Datasheets (PDF)
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- `ESP32-PICO-D4 <https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf>`_
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- `ESP32-PICO-V3 <https://www.espressif.com/sites/default/files/documentation/esp32-pico-v3_datasheet_en.pdf>`_
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- `ESP32-PICO-V3-02 <https://www.espressif.com/sites/default/files/documentation/esp32-pico-v3-02_datasheet_en.pdf>`_
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- `ESP32-S2 Datasheet (PDF) <https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf>`_
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- `ESP32-C3 Datasheet (PDF) <https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf>`_
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- `ESP32-S3 Datasheet (PDF) <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_
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- `ESP Product Selector <https://products.espressif.com/#/>`_ |