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https://github.com/espressif/esp-idf.git
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16677b0d3c
peripheral enable/disable usually should be managed by driver itself, so make it as espressif private APIs, not recommended for user to use it in application code. However, if user want to re-write the driver or ports to other platform, this is still possible by including the header in this way: "esp_private/peripheral_ctrl.h"
121 lines
5.2 KiB
C
121 lines
5.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "bootloader_random.h"
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#include "soc/rtc_periph.h"
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#include "soc/sens_periph.h"
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#include "soc/syscon_periph.h"
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#include "soc/dport_reg.h"
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#include "soc/i2s_periph.h"
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#include "esp_log.h"
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#include "soc/io_mux_reg.h"
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#ifndef BOOTLOADER_BUILD
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#include "esp_private/periph_ctrl.h"
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#endif
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void bootloader_random_enable(void)
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{
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/* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is
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never disabled while the CPU is running), this is a "belts and braces" type check.
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*/
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
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#else
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periph_module_enable(PERIPH_RNG_MODULE);
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#endif // BOOTLOADER_BUILD
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/* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
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reference via I2S into the RNG entropy input.
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Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M)
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in early bootloader startup must have been made.
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*/
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SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S);
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SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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#else
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periph_module_enable(PERIPH_I2S0_MODULE);
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#endif // BOOTLOADER_BUILD
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
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// Test pattern configuration byte 0xAD:
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//--[7:4] channel_sel: 10-->en_test
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//--[3:2] bit_width : 3-->12bit
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//--[1:0] atten : 1-->3dB attenuation
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
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SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX);
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SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S);
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S);
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SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S);
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SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL);
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CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
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SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
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SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
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SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
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SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
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SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
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}
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void bootloader_random_disable(void)
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{
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/* Reset some i2s configuration (possibly redundant as we reset entire
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I2S peripheral further down). */
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET);
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
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/* Disable i2s clock */
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#ifdef BOOTLOADER_BUILD
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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#else
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periph_module_disable(PERIPH_I2S0_MODULE);
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#endif // BOOTLOADER_BUILD
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/* Restore SYSCON mode registers */
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CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
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CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
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/* Restore SAR ADC mode */
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
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| SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
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/* Reset i2s peripheral */
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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#else
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periph_module_reset(PERIPH_I2S0_MODULE);
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#endif
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/* Disable pull supply voltage to SAR ADC */
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CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S);
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}
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