mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
f7ac13a566
because some LCD doesn't respond to that
151 lines
6.8 KiB
C
151 lines
6.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "soc/soc_caps.h"
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#include "esp_check.h"
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#include "esp_lcd_mipi_dsi.h"
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#include "esp_clk_tree.h"
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#include "mipi_dsi_priv.h"
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static const char *TAG = "lcd.dsi.bus";
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#define MIPI_DSI_DEFAULT_TIMEOUT_CLOCK_FREQ_MHZ 10
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// TxClkEsc frequency must be configured between 2 and 20 MHz
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#define MIPI_DSI_DEFAULT_ESCAPE_CLOCK_FREQ_MHZ 10
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esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lcd_dsi_bus_handle_t *ret_bus)
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{
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esp_err_t ret = ESP_OK;
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ESP_RETURN_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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ESP_RETURN_ON_FALSE(bus_config->num_data_lanes <= MIPI_DSI_LL_MAX_DATA_LANES,
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ESP_ERR_INVALID_ARG, TAG, "invalid number of data lanes %d", bus_config->num_data_lanes);
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ESP_RETURN_ON_FALSE(bus_config->lane_bit_rate_mbps >= MIPI_DSI_LL_MIN_PHY_MBPS &&
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bus_config->lane_bit_rate_mbps <= MIPI_DSI_LL_MAX_PHY_MBPS, ESP_ERR_INVALID_ARG, TAG,
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"invalid lane bit rate %"PRIu32, bus_config->lane_bit_rate_mbps);
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// we don't use an bus allocator here, because different DSI bus uses different PHY.
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// And each PHY has its own associated PINs, which is not changeable.
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// So user HAS TO specify the bus ID by themselves, according to their PCB design.
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int bus_id = bus_config->bus_id;
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ESP_RETURN_ON_FALSE(bus_id >= 0 && bus_id < MIPI_DSI_LL_NUM_BUS, ESP_ERR_INVALID_ARG, TAG, "invalid bus ID %d", bus_id);
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esp_lcd_dsi_bus_t *dsi_bus = heap_caps_calloc(1, sizeof(esp_lcd_dsi_bus_t), DSI_MEM_ALLOC_CAPS);
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ESP_RETURN_ON_FALSE(dsi_bus, ESP_ERR_NO_MEM, TAG, "no memory for DSI bus");
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dsi_bus->bus_id = bus_id;
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// Enable the APB clock for accessing the DSI host and bridge registers
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DSI_RCC_ATOMIC() {
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mipi_dsi_ll_enable_bus_clock(bus_id, true);
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mipi_dsi_ll_reset_register(bus_id);
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}
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// if the clock source is not assigned, fallback to the default clock source
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mipi_dsi_phy_clock_source_t phy_clk_src = bus_config->phy_clk_src;
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if (phy_clk_src == 0) {
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phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT;
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}
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// enable the clock source for DSI PHY
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DSI_CLOCK_SRC_ATOMIC() {
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// set clock source for DSI PHY
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mipi_dsi_ll_set_phy_clock_source(bus_id, phy_clk_src);
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// the configuration clock is used for all modes except the shutdown mode
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mipi_dsi_ll_enable_phy_config_clock(bus_id, true);
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// enable the clock for generating the serial clock
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mipi_dsi_ll_enable_phy_reference_clock(bus_id, true);
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}
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#if CONFIG_PM_ENABLE
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// When MIPI DSI is working, we don't expect the clock source would be turned off
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esp_pm_lock_type_t pm_lock_type = ESP_PM_NO_LIGHT_SLEEP;
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ret = esp_pm_lock_create(pm_lock_type, 0, "dsi_phy", &dsi_bus->pm_lock);
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ESP_GOTO_ON_ERROR(ret, err, TAG, "create PM lock failed");
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// before we configure the PLL, we want the clock source to be stable
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esp_pm_lock_acquire(dsi_bus->pm_lock);
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#endif
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// if the number of data lanes is not assigned, fallback to the maximum number of data lanes
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int num_data_lanes = bus_config->num_data_lanes;
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if (num_data_lanes == 0) {
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num_data_lanes = MIPI_DSI_LL_MAX_DATA_LANES;
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}
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// initialize HAL context
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mipi_dsi_hal_config_t hal_config = {
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.bus_id = bus_id,
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.lane_bit_rate_mbps = bus_config->lane_bit_rate_mbps,
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.num_data_lanes = num_data_lanes,
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};
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mipi_dsi_hal_init(&dsi_bus->hal, &hal_config);
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mipi_dsi_hal_context_t *hal = &dsi_bus->hal;
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// get the frequency of the PHY clock source
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uint32_t phy_clk_src_freq_hz = 0;
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ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(phy_clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
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&phy_clk_src_freq_hz), err, TAG, "get phy clock source frequency failed");
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// configure the PHY PLL
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mipi_dsi_hal_configure_phy_pll(hal, phy_clk_src_freq_hz, bus_config->lane_bit_rate_mbps);
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// wait for PHY initialization done
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while (!mipi_dsi_phy_ll_is_pll_locked(hal->host)) {
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vTaskDelay(pdMS_TO_TICKS(1));
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}
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while (!mipi_dsi_phy_ll_are_lanes_stopped(hal->host, num_data_lanes)) {
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vTaskDelay(pdMS_TO_TICKS(1));
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}
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// initialize the DSI operation mode: command mode
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mipi_dsi_host_ll_enable_video_mode(hal->host, false);
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// place the clock lane in low power mode, we will switch to high speed mode later when DPI stream is ready
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mipi_dsi_host_ll_set_clock_lane_state(hal->host, MIPI_DSI_LL_CLOCK_LANE_STATE_LP);
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// Set the time that is required by the clock and data lanes to go from high-speed to low-power and from low-power to high-speed
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mipi_dsi_phy_ll_set_switch_time(hal->host, 50, 104, 46, 128);
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// enable CRC reception and ECC reception, error correction, and reporting
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mipi_dsi_host_ll_enable_rx_crc(hal->host, true);
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mipi_dsi_host_ll_enable_rx_ecc(hal->host, true);
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// enable sending the EoTp packet at the end of each transmission for HS mode
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mipi_dsi_host_ll_enable_tx_eotp(hal->host, true, false);
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// Set the divider to get the Time Out clock, clock source is the high-speed byte clock
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mipi_dsi_host_ll_set_timeout_clock_division(hal->host, bus_config->lane_bit_rate_mbps / 8 / MIPI_DSI_DEFAULT_TIMEOUT_CLOCK_FREQ_MHZ);
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// Set the divider to get the TX Escape clock, clock source is the high-speed byte clock
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mipi_dsi_host_ll_set_escape_clock_division(hal->host, bus_config->lane_bit_rate_mbps / 8 / MIPI_DSI_DEFAULT_ESCAPE_CLOCK_FREQ_MHZ);
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// set the timeout intervals to zero, means to disable the timeout mechanism
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mipi_dsi_host_ll_set_timeout_count(hal->host, 0, 0, 0, 0, 0, 0, 0);
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// DSI host will wait indefinitely for a read response from the DSI device
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mipi_dsi_phy_ll_set_max_read_time(hal->host, 6000);
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// set how long the DSI host will wait before sending the next transmission
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mipi_dsi_phy_ll_set_stop_wait_time(hal->host, 0x3F);
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*ret_bus = dsi_bus;
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return ESP_OK;
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err:
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if (dsi_bus) {
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esp_lcd_del_dsi_bus(dsi_bus);
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}
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return ret;
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}
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esp_err_t esp_lcd_del_dsi_bus(esp_lcd_dsi_bus_handle_t bus)
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{
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ESP_RETURN_ON_FALSE(bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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int bus_id = bus->bus_id;
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// disable the clock source for DSI PHY
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DSI_CLOCK_SRC_ATOMIC() {
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mipi_dsi_ll_enable_phy_reference_clock(bus_id, false);
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mipi_dsi_ll_enable_phy_config_clock(bus_id, false);
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}
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// disable the APB clock for accessing the DSI peripheral registers
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DSI_RCC_ATOMIC() {
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mipi_dsi_ll_enable_bus_clock(bus_id, false);
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}
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if (bus->pm_lock) {
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esp_pm_lock_release(bus->pm_lock);
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esp_pm_lock_delete(bus->pm_lock);
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}
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free(bus);
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return ESP_OK;
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}
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