mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
781d06af73
This function removes the following legacy atomic CAS functions: From compare_set.h (file removed): - compare_and_set_native() - compare_and_set_extram() From portmacro.h - uxPortCompareSet() - uxPortCompareSetExtram() Users should call esp_cpu_compare_and_set() instead as this function hides the details of atomic CAS on internal and external RAM addresses. Due to the removal of compare_set.h, some missing header includes are also fixed in this commit.
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <unity.h>
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#include <spi_flash_mmap.h>
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#include <esp_attr.h>
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#include <esp_flash_encrypt.h>
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#include "esp_memory_utils.h"
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#include "esp_private/cache_utils.h"
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static QueueHandle_t result_queue;
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static IRAM_ATTR void cache_test_task(void *arg)
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{
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bool do_disable = (bool)arg;
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bool result;
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if(do_disable) {
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spi_flash_disable_interrupts_caches_and_other_cpu();
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}
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result = spi_flash_cache_enabled();
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if (do_disable) {
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spi_flash_enable_interrupts_caches_and_other_cpu();
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}
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TEST_ASSERT( xQueueSendToBack(result_queue, &result, 0) );
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vTaskDelete(NULL);
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}
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TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash]")
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{
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result_queue = xQueueCreate(1, sizeof(bool));
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for(int cpu = 0; cpu < portNUM_PROCESSORS; cpu++) {
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for(int disable = 0; disable <= 1; disable++) {
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bool do_disable = disable;
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bool result;
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printf("Testing cpu %d disabled %d\n", cpu, do_disable);
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xTaskCreatePinnedToCore(cache_test_task, "cache_check_task",
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2048, (void *)do_disable, configMAX_PRIORITIES-1, NULL, cpu);
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TEST_ASSERT( xQueueReceive(result_queue, &result, 2) );
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TEST_ASSERT_EQUAL(!do_disable, result);
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}
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}
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vQueueDelete(result_queue);
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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// This needs to sufficiently large array, otherwise it may end up in
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// DRAM (e.g. size <= 8 bytes && ARCH == RISCV)
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static const uint32_t s_in_rodata[8] = { 0x12345678, 0xfedcba98 };
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static void IRAM_ATTR cache_access_test_func(void* arg)
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{
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/* Assert that the array s_in_rodata is in DROM. If not, this test is
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* invalid as disabling the cache wouldn't have any effect. */
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TEST_ASSERT(esp_ptr_in_drom(s_in_rodata));
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spi_flash_disable_interrupts_caches_and_other_cpu();
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volatile uint32_t* src = (volatile uint32_t*) s_in_rodata;
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uint32_t v1 = src[0];
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uint32_t v2 = src[1];
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bool cache_enabled = spi_flash_cache_enabled();
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spi_flash_enable_interrupts_caches_and_other_cpu();
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printf("%d %x %x\n", cache_enabled, v1, v2);
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vTaskDelete(NULL);
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}
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#if CONFIG_IDF_TARGET_ESP32
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#define CACHE_ERROR_REASON "Cache disabled,SW_RESET"
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2
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#define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST"
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#endif
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// These tests works properly if they resets the chip with the
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// "Cache disabled but cached memory region accessed" reason and the correct CPU is logged.
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TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]")
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{
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xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0);
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vTaskDelay(1000/portTICK_PERIOD_MS);
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]")
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{
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xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 1);
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vTaskDelay(1000/portTICK_PERIOD_MS);
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}
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#endif // !CONFIG_FREERTOS_UNICORE
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#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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