mirror of
https://github.com/espressif/esp-idf.git
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e25cda2c40
For RISC-V and Xtensa targets, in case a panic needs to happen when Task WDT is triggered (ESP_TASK_WDT_PANIC), the interruptee's stack is now used for printing the backtrace. Abort after Task Watchdog is triggered can happen on APP CPU (second core).
428 lines
14 KiB
C
428 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "esp_private/system_internal.h"
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#include "esp_private/usb_console.h"
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#include "esp_cpu.h"
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#include "soc/rtc.h"
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#include "hal/timer_hal.h"
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#include "hal/wdt_types.h"
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#include "hal/wdt_hal.h"
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#include "esp_private/panic_internal.h"
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#include "port/panic_funcs.h"
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#include "esp_rom_sys.h"
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#include "sdkconfig.h"
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#if __has_include("esp_ota_ops.h")
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#include "esp_ota_ops.h"
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#define HAS_ESP_OTA 1
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#endif
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#if CONFIG_ESP_COREDUMP_ENABLE
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#include "esp_core_dump.h"
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#endif
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#if CONFIG_APPTRACE_ENABLE
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#include "esp_app_trace.h"
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#if CONFIG_APPTRACE_SV_ENABLE
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#include "SEGGER_RTT.h"
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#endif
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#if CONFIG_APPTRACE_ONPANIC_HOST_FLUSH_TMO == -1
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#define APPTRACE_ONPANIC_HOST_FLUSH_TMO ESP_APPTRACE_TMO_INFINITE
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#else
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#define APPTRACE_ONPANIC_HOST_FLUSH_TMO (1000*CONFIG_APPTRACE_ONPANIC_HOST_FLUSH_TMO)
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#endif
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#endif // CONFIG_APPTRACE_ENABLE
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#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
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#include "hal/uart_hal.h"
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#endif
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#if CONFIG_ESP_SYSTEM_PANIC_GDBSTUB
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#include "esp_gdbstub.h"
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#endif
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#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
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#include "hal/usb_serial_jtag_ll.h"
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#endif
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bool g_panic_abort = false;
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static char *s_panic_abort_details = NULL;
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static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
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#if CONFIG_ESP_CONSOLE_UART
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static uart_hal_context_t s_panic_uart = { .dev = CONFIG_ESP_CONSOLE_UART_NUM == 0 ? &UART0 :&UART1 };
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void panic_print_char(const char c)
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{
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uint32_t sz = 0;
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while (!uart_hal_get_txfifo_len(&s_panic_uart));
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uart_hal_write_txfifo(&s_panic_uart, (uint8_t *) &c, 1, &sz);
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}
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#endif // CONFIG_ESP_CONSOLE_UART
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#if CONFIG_ESP_CONSOLE_USB_CDC
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void panic_print_char(const char c)
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{
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esp_usb_console_write_buf(&c, 1);
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/* result ignored */
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}
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#endif // CONFIG_ESP_CONSOLE_USB_CDC
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#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
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//Timeout; if there's no host listening, the txfifo won't ever
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//be writable after the first packet.
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#define USBSERIAL_TIMEOUT_MAX_US 50000
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static int s_usbserial_timeout = 0;
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void panic_print_char(const char c)
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{
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while (!usb_serial_jtag_ll_txfifo_writable() && s_usbserial_timeout < (USBSERIAL_TIMEOUT_MAX_US / 100)) {
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esp_rom_delay_us(100);
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s_usbserial_timeout++;
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}
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if (usb_serial_jtag_ll_txfifo_writable()) {
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usb_serial_jtag_ll_write_txfifo((const uint8_t *)&c, 1);
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s_usbserial_timeout = 0;
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}
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}
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#endif //CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
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#if CONFIG_ESP_CONSOLE_NONE
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void panic_print_char(const char c)
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{
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/* no-op */
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}
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#endif // CONFIG_ESP_CONSOLE_NONE
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void panic_print_str(const char *str)
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{
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for (int i = 0; str[i] != 0; i++) {
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panic_print_char(str[i]);
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}
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}
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void panic_print_hex(int h)
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{
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int x;
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int c;
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// Does not print '0x', only the digits (8 digits to print)
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for (x = 0; x < 8; x++) {
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c = (h >> 28) & 0xf; // extract the leftmost byte
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if (c < 10) {
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panic_print_char('0' + c);
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} else {
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panic_print_char('a' + c - 10);
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}
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h <<= 4; // move the 2nd leftmost byte to the left, to be extracted next
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}
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}
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void panic_print_dec(int d)
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{
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// can print at most 2 digits!
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int n1, n2;
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n1 = d % 10; // extract ones digit
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n2 = d / 10; // extract tens digit
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if (n2 == 0) {
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panic_print_char(' ');
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} else {
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panic_print_char(n2 + '0');
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}
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panic_print_char(n1 + '0');
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}
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#endif // CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
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/*
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If watchdogs are enabled, the panic handler runs the risk of getting aborted pre-emptively because
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an overzealous watchdog decides to reset it. On the other hand, if we disable all watchdogs, we run
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the risk of somehow halting in the panic handler and not resetting. That is why this routine kills
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all watchdogs except the timer group 0 watchdog, and it reconfigures that to reset the chip after
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one second.
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We have to do this before we do anything that might cause issues in the WDT interrupt handlers,
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for example stalling the other core on ESP32 may cause the ESP32_ECO3_CACHE_LOCK_FIX
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handler to get stuck.
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*/
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void esp_panic_handler_reconfigure_wdts(void)
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{
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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#if SOC_TIMER_GROUPS >= 2
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// IDF-3825
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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#endif
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//Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
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//Reconfigure TWDT (Timer Group 0)
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wdt_hal_init(&wdt0_context, WDT_MWDT0, MWDT0_TICK_PRESCALER, false); //Prescaler: wdt counts in ticks of TG0_WDT_TICK_US
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_config_stage(&wdt0_context, 0, 1000 * 1000 / MWDT0_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //1 second before reset
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wdt_hal_enable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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#if SOC_TIMER_GROUPS >= 2
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//Disable IWDT (Timer Group 1)
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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#endif
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}
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/*
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This disables all the watchdogs for when we call the gdbstub.
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*/
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static inline void disable_all_wdts(void)
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{
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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#if SOC_TIMER_GROUPS >= 2
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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#endif
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//Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
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//Task WDT is the Main Watchdog Timer of Timer Group 0
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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#if SOC_TIMER_GROUPS >= 2
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//Interupt WDT is the Main Watchdog Timer of Timer Group 1
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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#endif
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}
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static void print_abort_details(const void *f)
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{
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panic_print_str(s_panic_abort_details);
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}
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// Control arrives from chip-specific panic handler, environment prepared for
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// the 'main' logic of panic handling. This means that chip-specific stuff have
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// already been done, and panic_info_t has been filled.
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void esp_panic_handler(panic_info_t *info)
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{
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// The port-level panic handler has already called this, but call it again
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// to reset the TG0WDT period
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esp_panic_handler_reconfigure_wdts();
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// If the exception was due to an abort, override some of the panic info
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if (g_panic_abort) {
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info->description = NULL;
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info->details = s_panic_abort_details ? print_abort_details : NULL;
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info->reason = NULL;
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info->exception = PANIC_EXCEPTION_ABORT;
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}
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/*
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* For any supported chip, the panic handler prints the contents of panic_info_t in the following format:
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*
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*
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* Guru Meditation Error: Core <core> (<exception>). <description>
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* <details>
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*
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* <state>
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*
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* <elf_info>
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*
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*
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* ----------------------------------------------------------------------------------------
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* core - core where exception was triggered
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* exception - what kind of exception occured
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* description - a short description regarding the exception that occured
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* details - more details about the exception
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* state - processor state like register contents, and backtrace
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* elf_info - details about the image currently running
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*
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* NULL fields in panic_info_t are not printed.
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*
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* */
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if (info->reason) {
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panic_print_str("Guru Meditation Error: Core ");
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panic_print_dec(info->core);
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panic_print_str(" panic'ed (");
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panic_print_str(info->reason);
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panic_print_str("). ");
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}
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if (info->description) {
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panic_print_str(info->description);
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}
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panic_print_str("\r\n");
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PANIC_INFO_DUMP(info, details);
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panic_print_str("\r\n");
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// If on-chip-debugger is attached, and system is configured to be aware of this,
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// then only print up to details. Users should be able to probe for the other information
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// in debug mode.
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if (esp_cpu_dbgr_is_attached()) {
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panic_print_str("Setting breakpoint at 0x");
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panic_print_hex((uint32_t)info->addr);
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panic_print_str(" and returning...\r\n");
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disable_all_wdts();
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#if CONFIG_APPTRACE_ENABLE
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#if CONFIG_APPTRACE_SV_ENABLE
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SEGGER_RTT_ESP_FlushNoLock(CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#else
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH,
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APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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#endif
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esp_cpu_set_breakpoint(0, info->addr); // use breakpoint 0
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return;
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}
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// start panic WDT to restart system if we hang in this handler
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if (!wdt_hal_is_enabled(&rtc_wdt_ctx)) {
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = (uint32_t)(7000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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// 64KB of core dump data (stacks of about 30 tasks) will produce ~85KB base64 data.
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// @ 115200 UART speed it will take more than 6 sec to print them out.
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wdt_hal_enable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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}
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esp_panic_handler_reconfigure_wdts(); // Restart WDT again
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PANIC_INFO_DUMP(info, state);
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panic_print_str("\r\n");
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#if HAS_ESP_OTA
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panic_print_str("\r\nELF file SHA256: ");
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char sha256_buf[65];
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esp_ota_get_app_elf_sha256(sha256_buf, sizeof(sha256_buf));
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panic_print_str(sha256_buf);
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panic_print_str("\r\n");
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#endif //HAS_ESP_OTA
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panic_print_str("\r\n");
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#if CONFIG_APPTRACE_ENABLE
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disable_all_wdts();
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#if CONFIG_APPTRACE_SV_ENABLE
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SEGGER_RTT_ESP_FlushNoLock(CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#else
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH,
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APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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esp_panic_handler_reconfigure_wdts(); // restore WDT config
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#endif // CONFIG_APPTRACE_ENABLE
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#if CONFIG_ESP_SYSTEM_PANIC_GDBSTUB
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disable_all_wdts();
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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panic_print_str("Entering gdb stub now.\r\n");
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esp_gdbstub_panic_handler((void *)info->frame);
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#else
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#if CONFIG_ESP_COREDUMP_ENABLE
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static bool s_dumping_core;
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if (s_dumping_core) {
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panic_print_str("Re-entered core dump! Exception happened during core dump!\r\n");
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} else {
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disable_all_wdts();
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s_dumping_core = true;
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/* No matter if we come here from abort or an exception, this variable must be reset.
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* Else, any exception/error occuring during the current panic handler would considered
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* an abort. */
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g_panic_abort = false;
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#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH
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esp_core_dump_to_flash(info);
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#endif
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#if CONFIG_ESP_COREDUMP_ENABLE_TO_UART && !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
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esp_core_dump_to_uart(info);
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#endif
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s_dumping_core = false;
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esp_panic_handler_reconfigure_wdts();
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}
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#endif /* CONFIG_ESP_COREDUMP_ENABLE */
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#if CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT || CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
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if (esp_reset_reason_get_hint() == ESP_RST_UNKNOWN) {
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switch (info->exception) {
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case PANIC_EXCEPTION_IWDT:
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esp_reset_reason_set_hint(ESP_RST_INT_WDT);
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break;
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case PANIC_EXCEPTION_TWDT:
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esp_reset_reason_set_hint(ESP_RST_TASK_WDT);
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break;
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case PANIC_EXCEPTION_ABORT:
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case PANIC_EXCEPTION_FAULT:
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default:
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esp_reset_reason_set_hint(ESP_RST_PANIC);
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break; // do not touch the previously set reset reason hint
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}
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}
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panic_print_str("Rebooting...\r\n");
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panic_restart();
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#else
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disable_all_wdts();
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panic_print_str("CPU halted.\r\n");
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while (1);
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#endif /* CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT || CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT */
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#endif /* CONFIG_ESP_SYSTEM_PANIC_GDBSTUB */
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}
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void IRAM_ATTR __attribute__((noreturn, no_sanitize_undefined)) panic_abort(const char *details)
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{
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g_panic_abort = true;
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s_panic_abort_details = (char *) details;
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#if CONFIG_APPTRACE_ENABLE
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#if CONFIG_APPTRACE_SV_ENABLE
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SEGGER_RTT_ESP_FlushNoLock(CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#else
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, CONFIG_APPTRACE_POSTMORTEM_FLUSH_THRESH,
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APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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#endif
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*((volatile int *) 0) = 0; // NOLINT(clang-analyzer-core.NullDereference) should be an invalid operation on targets
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while (1);
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}
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/* Weak versions of reset reason hint functions.
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* If these weren't provided, reset reason code would be linked into the app
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* even if the app never called esp_reset_reason().
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*/
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void IRAM_ATTR __attribute__((weak)) esp_reset_reason_set_hint(esp_reset_reason_t hint)
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{
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}
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esp_reset_reason_t IRAM_ATTR __attribute__((weak)) esp_reset_reason_get_hint(void)
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{
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return ESP_RST_UNKNOWN;
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}
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