mirror of
https://github.com/espressif/esp-idf.git
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309 lines
9.8 KiB
C
309 lines
9.8 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_RMT_STRUCT_H_
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#define _SOC_RMT_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct {
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uint32_t data_ch[4]; /**/
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union {
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struct {
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uint32_t tx_start: 1;
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uint32_t mem_rd_rst: 1;
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uint32_t mem_rst: 1;
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uint32_t tx_conti_mode: 1;
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uint32_t mem_tx_wrap_en: 1;
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uint32_t idle_out_lv: 1;
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uint32_t idle_out_en: 1;
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uint32_t tx_stop: 1;
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uint32_t div_cnt: 8;
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uint32_t mem_size: 3;
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uint32_t reserved19: 1;
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uint32_t carrier_eff_en: 1;
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uint32_t carrier_en: 1;
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uint32_t carrier_out_lv: 1;
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uint32_t afifo_rst: 1;
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uint32_t conf_update: 1;
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uint32_t reserved25: 7;
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};
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uint32_t val;
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} tx_conf[2];
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struct {
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union {
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struct {
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uint32_t div_cnt: 8;
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uint32_t idle_thres: 15;
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uint32_t mem_size: 3;
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uint32_t reserved26: 2;
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uint32_t carrier_en: 1;
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uint32_t carrier_out_lv: 1;
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uint32_t reserved30: 2;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t rx_en: 1;
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uint32_t mem_wr_rst: 1;
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uint32_t mem_rst: 1;
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uint32_t mem_owner: 1;
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uint32_t rx_filter_en: 1;
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uint32_t rx_filter_thres: 8;
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uint32_t mem_rx_wrap_en: 1;
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uint32_t afifo_rst: 1;
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uint32_t conf_update: 1;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} conf1;
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} rx_conf[2];
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union {
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struct {
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uint32_t mem_raddr_ex: 9;
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uint32_t state: 3;
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uint32_t waddr: 9;
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uint32_t mem_rd_err: 1;
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uint32_t mem_empty: 1;
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uint32_t mem_wr_err: 1;
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uint32_t raddr: 8;
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};
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uint32_t val;
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} tx_status[2];
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union {
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struct {
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uint32_t mem_waddr_ex: 9;
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uint32_t reserved9: 3;
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uint32_t mem_raddr: 9;
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uint32_t reserved21: 1;
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uint32_t state: 3;
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uint32_t mem_owner_err: 1;
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uint32_t mem_full: 1;
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uint32_t mem_rd_err: 1;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} rx_status[2];
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t ch0_tx_end: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_rx_thr_event: 1;
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uint32_t ch3_rx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t low: 16;
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uint32_t high: 16;
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};
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uint32_t val;
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} tx_carrier[2];
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union {
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struct {
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uint32_t low_thres: 16;
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uint32_t high_thres: 16;
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};
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uint32_t val;
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} rx_carrier[2];
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union {
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struct {
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uint32_t limit: 9;
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uint32_t tx_loop_num: 10;
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uint32_t tx_loop_cnt_en: 1;
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uint32_t loop_count_reset: 1;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} tx_lim[2];
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union {
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struct {
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uint32_t rx_lim: 9;
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uint32_t reserved9: 23;
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};
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uint32_t val;
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} rx_lim[2];
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union {
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struct {
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uint32_t fifo_mask: 1;
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uint32_t mem_clk_force_on: 1;
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uint32_t mem_force_pd: 1;
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uint32_t mem_force_pu: 1;
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uint32_t sclk_div_num: 8;
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uint32_t sclk_div_a: 6;
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uint32_t sclk_div_b: 6;
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uint32_t sclk_sel: 2;
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uint32_t sclk_active: 1;
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uint32_t reserved27: 4;
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uint32_t clk_en: 1;
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};
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uint32_t val;
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} sys_conf;
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union {
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struct {
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uint32_t ch0: 1;
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uint32_t ch1: 1;
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uint32_t en: 1;
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uint32_t reserved3: 29;
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};
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uint32_t val;
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} tx_sim;
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union {
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struct {
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uint32_t ch0: 1;
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uint32_t ch1: 1;
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uint32_t ch2: 1;
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uint32_t ch3: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} ref_cnt_rst;
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uint32_t reserved_74;
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uint32_t reserved_78;
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uint32_t reserved_7c;
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uint32_t reserved_80;
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uint32_t reserved_84;
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uint32_t reserved_88;
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uint32_t reserved_8c;
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uint32_t reserved_90;
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uint32_t reserved_94;
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uint32_t reserved_98;
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uint32_t reserved_9c;
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uint32_t reserved_a0;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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union {
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struct {
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uint32_t date: 28;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} date;
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} rmt_dev_t;
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extern rmt_dev_t RMT;
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typedef struct {
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union {
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struct {
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uint32_t duration0 : 15;
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uint32_t level0 : 1;
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uint32_t duration1 : 15;
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uint32_t level1 : 1;
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};
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uint32_t val;
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};
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} rmt_item32_t;
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//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
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typedef volatile struct {
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struct {
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union {
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rmt_item32_t data32[48];
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};
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} chan[4];
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} rmt_mem_t;
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extern rmt_mem_t RMTMEM;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_RMT_STRUCT_H_ */
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