mirror of
https://github.com/espressif/esp-idf.git
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160 lines
5.6 KiB
C
160 lines
5.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <math.h>
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#include "soc/soc_caps.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "unity.h"
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#include "test_utils.h"
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#if SOC_CPU_HAS_FPU && CONFIG_FREERTOS_FPU_IN_ISR
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// We can use xtensa API here as currently, non of the RISC-V targets have an FPU
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#include "xtensa/xtensa_api.h"
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#include "esp_intr_alloc.h"
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#define SW_ISR_LEVEL_1 7
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static void fpu_isr(void *arg)
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{
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// Clear the interrupt
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xt_set_intclear(1 << SW_ISR_LEVEL_1);
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/*
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Use the FPU
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- We test using a calculation that will cause a change in mantissa and exponent for extra thoroughness
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- cosf(0.0f) should return 1.0f, thus we are simply doubling test_float every iteration.
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- Therefore, we should end up with (0.01) * (2^8) = 2.56 at the end of the loop
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*/
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volatile float test_float = 0.01f;
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for (int i = 0; i < 8; i++) {
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test_float = test_float * 2.0f * cosf(0.0f);
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}
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// We allow a 0.1% delta on the final result in case of any loss of precision from floating point calculations
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TEST_ASSERT_FLOAT_WITHIN(0.00256f, 2.56f, test_float);
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}
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/* ------------------------------------------------------------------------------------------------------------------ */
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/*
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Test FPU usage from a level 1 ISR
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Purpose:
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- Test that the FPU can be used from a level 1 ISR
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- Test that the ISR using the FPU does not corrupt the interrupted task's FPU context
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Procedure:
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- Allocate a level 1 ISR
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- Task uses the FPU then triggers the ISR
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- ISR uses the FPU as well (forcing the task's FPU context to be saved)
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- Task continues using the FPU (forcing its FPU context to be restored)
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Expected:
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- ISR should use the FPU without issue
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- The interrupted task can continue using the FPU without issue
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*/
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TEST_CASE("FPU: Usage in level 1 ISR", "[freertos]")
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{
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intr_handle_t isr_handle;
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TEST_ASSERT_EQUAL(ESP_OK, esp_intr_alloc(ETS_INTERNAL_SW0_INTR_SOURCE, ESP_INTR_FLAG_LEVEL1, &fpu_isr, NULL, &isr_handle));
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/*
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Use the FPU (calculate a different value than in the ISR)
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- We test using a calculation that will cause a change in mantissa and exponent for extra thoroughness
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- cosf(0.0f) should return 1.0f, thus we are simply dividing test_float every iteration.
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*/
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// We should end up with (2.56) / (2^4) = 0.16 at the end of the first loop
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volatile float test_float = 2.56f;
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for (int i = 0; i < 4; i++) {
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test_float = test_float / (2.0f * cosf(0.0f));
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}
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// We allow a 0.1% delta on the final result in case of any loss of precision from floating point calculations
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TEST_ASSERT_FLOAT_WITHIN(0.00016f, 0.16f, test_float);
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// Trigger the ISR
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xt_set_intset(1 << SW_ISR_LEVEL_1);
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// Continue using the FPU from a task context after the interrupt returns
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// We should end up with (0.16) / (2^4) = 0.01 at the end of the first loop
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for (int i = 0; i < 4; i++) {
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test_float = test_float / (2.0f * cosf(0.0f));
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}
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// We allow a 0.1% delta on the final result in case of any loss of precision from floating point calculations
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TEST_ASSERT_FLOAT_WITHIN(0.00001f, 0.01f, test_float);
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// Free the ISR
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esp_intr_free(isr_handle);
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}
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/* ------------------------------------------------------------------------------------------------------------------ */
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/*
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Test FPU usage in ISR does not affect an unpinned tasks
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Purpose:
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- Test that the ISR using the FPU will not affect the interrupted task's affinity
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Procedure:
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- Create an unpinned task
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- Unpinned task disables scheduling/preemption to ensure that it does not switch cores
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- Unpinned task allocates an ISR then triggers the ISR
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- The ISR interrupts the unpinned task then uses the FPU
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- Task reenables scheduling/preemption and cleans up
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Expected:
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- The ISR using the FPU will not affect the unpinned task's affinity
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*/
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static void unpinned_task(void *arg)
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{
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// Disable scheduling/preemption to make sure the current task doesn't switch cores
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#if CONFIG_FREERTOS_SMP
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vTaskPreemptionDisable(NULL);
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#else
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vTaskSuspendAll();
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#endif
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// Check that the task is unpinned
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#if CONFIG_FREERTOS_SMP
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TEST_ASSERT_EQUAL(tskNO_AFFINITY, vTaskCoreAffinityGet(NULL));
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#else
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TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetAffinity(NULL));
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#endif
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// Allocate an ISR to use the FPU
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intr_handle_t isr_handle;
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TEST_ASSERT_EQUAL(ESP_OK, esp_intr_alloc(ETS_INTERNAL_SW0_INTR_SOURCE, ESP_INTR_FLAG_LEVEL1, &fpu_isr, NULL, &isr_handle));
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// Trigger the ISR
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xt_set_intset(1 << SW_ISR_LEVEL_1);
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// Free the ISR
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esp_intr_free(isr_handle);
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// Task should remain unpinned after the ISR uses the FPU
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#if CONFIG_FREERTOS_SMP
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TEST_ASSERT_EQUAL(tskNO_AFFINITY, vTaskCoreAffinityGet(NULL));
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#else
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TEST_ASSERT_EQUAL(tskNO_AFFINITY, xTaskGetAffinity(NULL));
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#endif
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// Reenable scheduling/preemption
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#if CONFIG_FREERTOS_SMP
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vTaskPreemptionEnable(NULL);
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#else
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xTaskResumeAll();
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#endif
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// Indicate done and self delete
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xTaskNotifyGive((TaskHandle_t)arg);
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vTaskDelete(NULL);
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}
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TEST_CASE("FPU: Level 1 ISR does not affect unpinned task", "[freertos]")
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{
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TaskHandle_t unity_task_handle = xTaskGetCurrentTaskHandle();
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xTaskCreate(unpinned_task, "unpin", 2048, (void *)unity_task_handle, UNITY_FREERTOS_PRIORITY + 1, NULL);
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// Wait for task to complete
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ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
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vTaskDelay(10); // Short delay to allow task memory to be freed
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}
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#endif // SOC_CPU_HAS_FPU && CONFIG_FREERTOS_FPU_IN_ISR
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