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https://github.com/espressif/esp-idf.git
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92abac1fd8
As heap block may be allocated into multiple non-continuous chunks, to reserve enough memory for dma/internal usage, we do the malloc in the step of max available block.
348 lines
11 KiB
C
348 lines
11 KiB
C
/*
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Abstraction layer for spi-ram. For now, it's no more than a stub for the spiram_psram functions, but if
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we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
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*/
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <string.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp32s3/spiram.h"
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#include "spiram_psram.h"
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "soc/soc.h"
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#include "esp_heap_caps_init.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/dport_reg.h"
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#include "esp32s3/rom/cache.h"
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#include "soc/cache_memory.h"
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#include "soc/extmem_reg.h"
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#if CONFIG_SPIRAM
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static const char *TAG = "spiram";
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#if CONFIG_SPIRAM_SPEED_40M
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#define PSRAM_SPEED PSRAM_CACHE_S40M
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#else //#if CONFIG_SPIRAM_SPEED_80M
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#define PSRAM_SPEED PSRAM_CACHE_S80M
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#endif
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static bool s_spiram_inited = false;
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/*
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Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
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true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
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initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
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*/
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bool esp_spiram_test(void)
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{
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size_t spiram_size = esp_spiram_get_size();
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volatile int *spiram = (volatile int *)(SOC_EXTRAM_DATA_HIGH - spiram_size);
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size_t p;
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size_t s = spiram_size;
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int errct = 0;
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int initial_err = -1;
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if (SOC_EXTRAM_DATA_SIZE < spiram_size) {
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ESP_EARLY_LOGW(TAG, "Only test spiram from %08x to %08x\n", SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH);
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spiram = (volatile int *)SOC_EXTRAM_DATA_LOW;
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s = SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW;
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}
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for (p = 0; p < (s / sizeof(int)); p += 8) {
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spiram[p] = p ^ 0xAAAAAAAA;
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}
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for (p = 0; p < (s / sizeof(int)); p += 8) {
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if (spiram[p] != (p ^ 0xAAAAAAAA)) {
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errct++;
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if (errct == 1) {
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initial_err = p * 4;
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}
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if (errct < 4) {
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ESP_EARLY_LOGE(TAG, "SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p], p ^ 0xAAAAAAAA);
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}
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}
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}
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if (errct) {
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ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s / 32, initial_err + SOC_EXTRAM_DATA_LOW);
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return false;
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} else {
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ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
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return true;
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}
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}
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void IRAM_ATTR esp_spiram_init_cache(void)
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{
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size_t spiram_size = esp_spiram_get_size();
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Cache_Suspend_DCache();
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if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >= spiram_size) {
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Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - spiram_size, 0, 64, spiram_size >> 16, 0);
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} else {
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Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SOC_EXTRAM_DATA_HIGH - spiram_size, 0, 64, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) >> 16, 0);
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}
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REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS);
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#if !CONFIG_FREERTOS_UNICORE
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REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
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#endif
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Cache_Resume_DCache(0);
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}
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static uint32_t pages_for_flash = 0;
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static uint32_t instruction_in_spiram = 0;
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static uint32_t rodata_in_spiram = 0;
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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static int instr_flash2spiram_offs = 0;
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static uint32_t instr_start_page = 0;
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static uint32_t instr_end_page = 0;
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#endif
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#if CONFIG_SPIRAM_RODATA
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static int rodata_flash2spiram_offs = 0;
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static uint32_t rodata_start_page = 0;
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static uint32_t rodata_end_page = 0;
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#endif
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
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static uint32_t page0_mapped = 0;
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static uint32_t page0_page = INVALID_PHY_PAGE;
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#endif
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uint32_t esp_spiram_instruction_access_enabled(void)
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{
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return instruction_in_spiram;
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}
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uint32_t esp_spiram_rodata_access_enabled(void)
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{
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return rodata_in_spiram;
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}
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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esp_err_t esp_spiram_enable_instruction_access(void)
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{
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size_t spiram_size = esp_spiram_get_size();
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uint32_t pages_in_flash = 0;
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pages_in_flash += Cache_Count_Flash_Pages(CACHE_IBUS, &page0_mapped);
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if ((pages_in_flash + pages_for_flash) > (spiram_size >> 16)) {
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ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (spiram_size >> 16), (pages_in_flash + pages_for_flash));
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return ESP_FAIL;
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}
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ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM");
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uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START);
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instr_flash2spiram_offs = mmu_value - pages_for_flash;
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ESP_EARLY_LOGV(TAG, "Instructions from flash page%d copy to SPIRAM page%d, Offset: %d", mmu_value, pages_for_flash, instr_flash2spiram_offs);
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pages_for_flash = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, IRAM0_CACHE_ADDRESS_LOW, pages_for_flash, &page0_page);
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instruction_in_spiram = 1;
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return ESP_OK;
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}
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#endif
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#if CONFIG_SPIRAM_RODATA
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esp_err_t esp_spiram_enable_rodata_access(void)
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{
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size_t spiram_size = esp_spiram_get_size();
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uint32_t pages_in_flash = 0;
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pages_in_flash += Cache_Count_Flash_Pages(CACHE_DBUS, &page0_mapped);
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if ((pages_in_flash + pages_for_flash) > (spiram_size >> 16)) {
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ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the read only data.");
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return ESP_FAIL;
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}
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ESP_EARLY_LOGI(TAG, "Read only data copied and mapped to SPIRAM");
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uint32_t mmu_value = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START);
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rodata_flash2spiram_offs = mmu_value - pages_for_flash;
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ESP_EARLY_LOGV(TAG, "Rodata from flash page%d copy to SPIRAM page%d, Offset: %d", mmu_value, pages_for_flash, rodata_flash2spiram_offs);
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pages_for_flash = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, DRAM0_CACHE_ADDRESS_LOW, pages_for_flash, &page0_page);
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rodata_in_spiram = 1;
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return ESP_OK;
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}
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#endif
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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void instruction_flash_page_info_init(void)
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{
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uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
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instr_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START);
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instr_start_page &= MMU_ADDRESS_MASK;
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instr_end_page = instr_start_page + instr_page_cnt - 1;
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}
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uint32_t IRAM_ATTR instruction_flash_start_page_get(void)
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{
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return instr_start_page;
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}
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uint32_t IRAM_ATTR instruction_flash_end_page_get(void)
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{
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return instr_end_page;
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}
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int IRAM_ATTR instruction_flash2spiram_offset(void)
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{
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return instr_flash2spiram_offs;
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}
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#endif
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#if CONFIG_SPIRAM_RODATA
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void rodata_flash_page_info_init(void)
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{
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uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
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rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START);
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rodata_start_page &= MMU_ADDRESS_MASK;
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rodata_end_page = rodata_start_page + rodata_page_cnt - 1;
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}
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uint32_t IRAM_ATTR rodata_flash_start_page_get(void)
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{
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return rodata_start_page;
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}
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uint32_t IRAM_ATTR rodata_flash_end_page_get(void)
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{
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return rodata_end_page;
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}
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int IRAM_ATTR rodata_flash2spiram_offset(void)
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{
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return rodata_flash2spiram_offs;
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}
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#endif
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esp_err_t esp_spiram_init(void)
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{
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esp_err_t r;
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r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
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if (r != ESP_OK) {
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#if CONFIG_SPIRAM_IGNORE_NOTFOUND
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ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out.");
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#endif
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return r;
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}
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s_spiram_inited = true;
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#if (CONFIG_SPIRAM_SIZE != -1)
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if (esp_spiram_get_size() != CONFIG_SPIRAM_SIZE) {
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ESP_EARLY_LOGE(TAG, "Expected %dKiB chip but found %dKiB chip. Bailing out..", CONFIG_SPIRAM_SIZE / 1024, esp_spiram_get_size() / 1024);
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return ESP_ERR_INVALID_SIZE;
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}
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#endif
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ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device",
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(esp_spiram_get_size() * 8) / (1024 * 1024));
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ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_S40M ? "sram 40m" : "sram 80m");
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ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
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(PSRAM_MODE == PSRAM_VADDR_MODE_EVENODD) ? "even/odd (2-core)" : \
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(PSRAM_MODE == PSRAM_VADDR_MODE_LOWHIGH) ? "low/high (2-core)" : \
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(PSRAM_MODE == PSRAM_VADDR_MODE_NORMAL) ? "normal (1-core)" : "ERROR");
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return ESP_OK;
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}
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esp_err_t esp_spiram_add_to_heapalloc(void)
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{
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size_t spiram_size = esp_spiram_get_size();
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uint32_t size_for_flash = (pages_for_flash << 16);
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ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (spiram_size - (pages_for_flash << 16)) / 1024);
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//Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
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//no need to explicitly specify them.
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return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_HIGH - spiram_size + size_for_flash, (intptr_t)SOC_EXTRAM_DATA_HIGH - 1);
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}
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esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
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if (size == 0) {
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return ESP_OK;
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}
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ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024);
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/* Pool may be allocated in multiple non-contiguous chunks, depending on available RAM */
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while (size > 0) {
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size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
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next_size = MIN(next_size, size);
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ESP_EARLY_LOGD(TAG, "Allocating block of size %d bytes", next_size);
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uint8_t *dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
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if (!dma_heap || next_size == 0) {
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return ESP_ERR_NO_MEM;
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}
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uint32_t caps[] = { 0, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT };
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esp_err_t e = heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+next_size-1);
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if (e != ESP_OK) {
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return e;
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}
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size -= next_size;
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}
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return ESP_OK;
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}
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size_t esp_spiram_get_size(void)
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{
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if (!s_spiram_inited) {
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ESP_EARLY_LOGE(TAG, "SPI RAM not initialized");
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abort();
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}
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psram_size_t size = psram_get_size();
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if (size == PSRAM_SIZE_16MBITS) {
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return 2 * 1024 * 1024;
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}
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if (size == PSRAM_SIZE_32MBITS) {
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return 4 * 1024 * 1024;
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}
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if (size == PSRAM_SIZE_64MBITS) {
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return 8 * 1024 * 1024;
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}
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if (size == PSRAM_SIZE_128MBITS) {
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return 16 * 1024 * 1024;
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}
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if (size == PSRAM_SIZE_256MBITS) {
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return 32 * 1024 * 1024;
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}
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return CONFIG_SPIRAM_SIZE;
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}
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/*
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Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
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otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
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*/
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void IRAM_ATTR esp_spiram_writeback_cache(void)
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{
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extern void Cache_WriteBack_All(void);
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Cache_WriteBack_All();
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}
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/**
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* @brief If SPI RAM(PSRAM) has been initialized
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*
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* @return true SPI RAM has been initialized successfully
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* @return false SPI RAM hasn't been initialized or initialized failed
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*/
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bool esp_spiram_is_initialized(void)
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{
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return s_spiram_inited;
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}
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uint8_t esp_spiram_get_cs_io(void)
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{
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return psram_get_cs_io();
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}
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#endif
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