mirror of
https://github.com/espressif/esp-idf.git
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560 lines
17 KiB
C
560 lines
17 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Register */
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/** Type of external_device_encrypt_decrypt_control register
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* External device encryption/decryption configuration register
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*/
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typedef union {
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struct {
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/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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uint32_t enable_spi_manual_encrypt:1;
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/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
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* reserved
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*/
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uint32_t enable_download_db_encrypt:1;
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/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
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* Configures whether or not to enable MSPI XTS auto decryption in download boot
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* mode.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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uint32_t enable_download_g0cb_decrypt:1;
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/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
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* Configures whether or not to enable MSPI XTS manual encryption in download boot
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* mode. \\
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* 0: Disable\\
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* 1: Enable\\
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*/
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uint32_t enable_download_manual_encrypt:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} hp_system_external_device_encrypt_decrypt_control_reg_t;
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/** Type of sram_usage_conf register
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* HP memory usage configuration register
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*/
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typedef union {
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struct {
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/** cache_usage : HRO; bitpos: [0]; default: 0;
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* reserved
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*/
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uint32_t cache_usage:1;
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uint32_t reserved_1:7;
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/** sram_usage : R/W; bitpos: [11:8]; default: 0;
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* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
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*/
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uint32_t sram_usage:4;
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uint32_t reserved_12:4;
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/** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
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* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
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*/
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uint32_t mac_dump_alloc:1;
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uint32_t reserved_17:15;
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};
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uint32_t val;
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} hp_system_sram_usage_conf_reg_t;
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/** Type of sec_dpa_conf register
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* HP anti-DPA security configuration register
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*/
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typedef union {
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struct {
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/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to enable anti-DPA attack. Valid only when
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* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
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* 0: Disable\\
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* 1-3: Enable. The larger the number, the higher the security level, which represents
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* the ability to resist DPA attacks, with increased computational overhead of the
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* hardware crypto-accelerators at the same time. \\
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*/
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uint32_t sec_dpa_level:2;
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/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
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* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
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* eFuse) to control DPA level. \\
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* 0: Select EFUSE_SEC_DPA_LEVEL\\
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* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
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*/
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uint32_t sec_dpa_cfg_sel:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} hp_system_sec_dpa_conf_reg_t;
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/** Type of sdio_ctrl register
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* SDIO Control configuration register
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*/
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typedef union {
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struct {
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/** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
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* Set this bit as 1 to disable SDIO_PROB function. disable by default.
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*/
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uint32_t dis_sdio_prob:1;
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/** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
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* Enable sdio slave to access other peripherals on the chip
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*/
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uint32_t sdio_win_access_en:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} hp_system_sdio_ctrl_reg_t;
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/** Type of rom_table_lock register
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* ROM-Table lock register
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*/
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typedef union {
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struct {
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/** rom_table_lock : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
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* 0: Unlock \\
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* 1: Lock \\
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*/
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uint32_t rom_table_lock:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_system_rom_table_lock_reg_t;
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/** Type of rom_table register
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* ROM-Table register
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*/
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typedef union {
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struct {
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/** rom_table : R/W; bitpos: [31:0]; default: 0;
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* Software ROM-Table register, whose content can be modified only when
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* HP_SYSTEM_ROM_TABLE_LOCK is 0.
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*/
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uint32_t rom_table:32;
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};
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uint32_t val;
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} hp_system_rom_table_reg_t;
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/** Type of core_debug_runstall_conf register
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* Core Debug RunStall configurion register
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*/
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typedef union {
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struct {
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/** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to enable debug RunStall functionality between HP CPU and
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* LP CPU.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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uint32_t core_debug_runstall_enable:1;
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/** core_runstalled : RO; bitpos: [1]; default: 0;
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* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
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* not stalled.
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*/
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uint32_t core_runstalled:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} hp_system_core_debug_runstall_conf_reg_t;
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/** Type of mem_test_conf register
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* MEM_TEST configuration register
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*/
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typedef union {
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struct {
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/** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
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* This field controls hp system memory WPULSE parameter.
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*/
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uint32_t hp_mem_wpulse:3;
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/** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
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* This field controls hp system memory WA parameter.
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*/
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uint32_t hp_mem_wa:3;
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/** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
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* This field controls hp system memory RA parameter.
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*/
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uint32_t hp_mem_ra:2;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} hp_system_mem_test_conf_reg_t;
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/** Type of sprom_ctrl register
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* reserved
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*/
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typedef union {
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struct {
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/** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
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* reserved
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*/
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uint32_t sprom_mem_aux_ctrl:32;
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};
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uint32_t val;
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} hp_system_sprom_ctrl_reg_t;
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/** Type of spram_ctrl register
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* reserved
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*/
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typedef union {
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struct {
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/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
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* reserved
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*/
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uint32_t spram_mem_aux_ctrl:32;
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};
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uint32_t val;
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} hp_system_spram_ctrl_reg_t;
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/** Type of sprf_ctrl register
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* reserved
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*/
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typedef union {
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struct {
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/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
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* reserved
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*/
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uint32_t sprf_mem_aux_ctrl:32;
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};
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uint32_t val;
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} hp_system_sprf_ctrl_reg_t;
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/** Type of sdprf_ctrl register
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* reserved
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*/
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typedef union {
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struct {
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/** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
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* reserved
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*/
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uint32_t sdprf_mem_aux_ctrl:32;
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};
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uint32_t val;
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} hp_system_sdprf_ctrl_reg_t;
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/** Type of bitscrambler_peri_sel register
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* reserved
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*/
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typedef union {
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struct {
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/** bitscrambler_rx_sel : R/W; bitpos: [3:0]; default: 0;
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* select peri that will be connected to bitscrambler,dir : receive data from bs
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*/
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uint32_t bitscrambler_rx_sel:4;
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/** bitscrambler_tx_sel : R/W; bitpos: [7:4]; default: 0;
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* select peri that will be connected to bitscrambler,dir : transfer data to peri
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*/
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uint32_t bitscrambler_tx_sel:4;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} hp_system_bitscrambler_peri_sel_reg_t;
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/** Type of clock_gate register
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* HP-SYSTEM clock gating configure register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 0;
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* Set this bit as 1 to force on clock gating.
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_system_clock_gate_reg_t;
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/** Group: Timeout Register */
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/** Type of cpu_peri_timeout_conf register
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* CPU_PERI_TIMEOUT configuration register
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*/
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typedef union {
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struct {
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/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
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* Configures the timeout threshold for bus access for accessing CPU peripheral
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* register in the number of clock cycles of the clock domain.
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*/
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uint32_t cpu_peri_timeout_thres:16;
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/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
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* Write 1 to clear timeout interrupt.
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*/
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uint32_t cpu_peri_timeout_int_clear:1;
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/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
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* Configures whether or not to enable timeout protection for accessing CPU peripheral
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* registers.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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uint32_t cpu_peri_timeout_protect_en:1;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} hp_system_cpu_peri_timeout_conf_reg_t;
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/** Type of cpu_peri_timeout_addr register
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* CPU_PERI_TIMEOUT_ADDR register
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*/
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typedef union {
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struct {
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/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
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* Represents the address information of abnormal access.
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*/
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uint32_t cpu_peri_timeout_addr:32;
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};
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uint32_t val;
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} hp_system_cpu_peri_timeout_addr_reg_t;
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/** Type of cpu_peri_timeout_uid register
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* CPU_PERI_TIMEOUT_UID register
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*/
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typedef union {
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struct {
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/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
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* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
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* register will be cleared after the interrupt is cleared.
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*/
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uint32_t cpu_peri_timeout_uid:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} hp_system_cpu_peri_timeout_uid_reg_t;
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/** Type of hp_peri_timeout_conf register
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* HP_PERI_TIMEOUT configuration register
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*/
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typedef union {
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struct {
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/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
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* Configures the timeout threshold for bus access for accessing HP peripheral
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* register, corresponding to the number of clock cycles of the clock domain.
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*/
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uint32_t hp_peri_timeout_thres:16;
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/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
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* Configures whether or not to clear timeout interrupt.\\
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* 0: No effect\\
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* 1: Clear timeout interrupt\\
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*/
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uint32_t hp_peri_timeout_int_clear:1;
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/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
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* Configures whether or not to enable timeout protection for accessing HP peripheral
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* registers.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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uint32_t hp_peri_timeout_protect_en:1;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} hp_system_hp_peri_timeout_conf_reg_t;
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/** Type of hp_peri_timeout_addr register
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* HP_PERI_TIMEOUT_ADDR register
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*/
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typedef union {
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struct {
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/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
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* Represents the address information of abnormal access.
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*/
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uint32_t hp_peri_timeout_addr:32;
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};
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uint32_t val;
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} hp_system_hp_peri_timeout_addr_reg_t;
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/** Type of hp_peri_timeout_uid register
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* HP_PERI_TIMEOUT_UID register
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*/
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typedef union {
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struct {
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/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
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* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
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* register will be cleared after the interrupt is cleared.
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*/
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uint32_t hp_peri_timeout_uid:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} hp_system_hp_peri_timeout_uid_reg_t;
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/** Type of modem_peri_timeout_conf register
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* MODEM_PERI_TIMEOUT configuration register
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*/
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typedef union {
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struct {
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/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
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* Set the timeout threshold for bus access, corresponding to the number of clock
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* cycles of the clock domain.
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*/
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uint32_t modem_peri_timeout_thres:16;
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/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
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* Set this bit as 1 to clear timeout interrupt
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*/
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uint32_t modem_peri_timeout_int_clear:1;
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/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
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* Set this bit as 1 to enable timeout protection for accessing modem registers
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*/
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uint32_t modem_peri_timeout_protect_en:1;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} hp_system_modem_peri_timeout_conf_reg_t;
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/** Type of modem_peri_timeout_addr register
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* MODEM_PERI_TIMEOUT_ADDR register
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*/
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typedef union {
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struct {
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/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
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* Record the address information of abnormal access
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*/
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uint32_t modem_peri_timeout_addr:32;
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};
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uint32_t val;
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} hp_system_modem_peri_timeout_addr_reg_t;
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/** Type of modem_peri_timeout_uid register
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* MODEM_PERI_TIMEOUT_UID register
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*/
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typedef union {
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struct {
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/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
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* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
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* will be cleared after the interrupt is cleared.
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*/
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uint32_t modem_peri_timeout_uid:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} hp_system_modem_peri_timeout_uid_reg_t;
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/** Group: Redcy ECO Registers */
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/** Type of rnd_eco register
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* redcy eco register.
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*/
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typedef union {
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struct {
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/** redcy_ena : W/R; bitpos: [0]; default: 0;
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* Only reserved for ECO.
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*/
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uint32_t redcy_ena:1;
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/** redcy_result : RO; bitpos: [1]; default: 0;
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* Only reserved for ECO.
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*/
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uint32_t redcy_result:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} hp_system_rnd_eco_reg_t;
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/** Type of rnd_eco_low register
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* redcy eco low register.
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*/
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typedef union {
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struct {
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/** redcy_low : W/R; bitpos: [31:0]; default: 0;
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* Only reserved for ECO.
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*/
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uint32_t redcy_low:32;
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};
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uint32_t val;
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} hp_system_rnd_eco_low_reg_t;
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/** Type of rnd_eco_high register
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* redcy eco high register.
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*/
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typedef union {
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struct {
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/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
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* Only reserved for ECO.
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*/
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uint32_t redcy_high:32;
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};
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uint32_t val;
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} hp_system_rnd_eco_high_reg_t;
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/** Group: Debug Register */
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/** Type of debug register
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* HP-SYSTEM debug register
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*/
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typedef union {
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struct {
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/** fpga_debug : R/W; bitpos: [0]; default: 1;
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* Reserved
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*/
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uint32_t fpga_debug:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} hp_system_debug_reg_t;
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|
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/** Group: Version Register */
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/** Type of date register
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* Date control and version control register
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*/
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typedef union {
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|
struct {
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/** date : R/W; bitpos: [27:0]; default: 36774016;
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* Version control register.
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|
*/
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|
uint32_t date:28;
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|
uint32_t reserved_28:4;
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};
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|
uint32_t val;
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} hp_system_date_reg_t;
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|
|
|
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typedef struct {
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volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
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volatile hp_system_sram_usage_conf_reg_t sram_usage_conf;
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|
volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf;
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volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
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volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
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|
volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
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volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
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volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
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|
volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
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|
volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
|
|
volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
|
|
volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
|
|
volatile hp_system_sdio_ctrl_reg_t sdio_ctrl;
|
|
uint32_t reserved_034;
|
|
volatile hp_system_rom_table_lock_reg_t rom_table_lock;
|
|
volatile hp_system_rom_table_reg_t rom_table;
|
|
volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
|
|
volatile hp_system_mem_test_conf_reg_t mem_test_conf;
|
|
uint32_t reserved_048[10];
|
|
volatile hp_system_sprom_ctrl_reg_t sprom_ctrl;
|
|
volatile hp_system_spram_ctrl_reg_t spram_ctrl;
|
|
volatile hp_system_sprf_ctrl_reg_t sprf_ctrl;
|
|
volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl;
|
|
volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
|
|
uint32_t reserved_084[215];
|
|
volatile hp_system_rnd_eco_reg_t rnd_eco;
|
|
volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
|
|
volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;
|
|
uint32_t reserved_3ec[2];
|
|
volatile hp_system_debug_reg_t debug;
|
|
volatile hp_system_clock_gate_reg_t clock_gate;
|
|
volatile hp_system_date_reg_t date;
|
|
} hp_system_dev_t;
|
|
|
|
extern hp_system_dev_t HP_SYSTEM;
|
|
|
|
#ifndef __cplusplus
|
|
_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
|
|
#endif
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|