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27470afb7c
update gpio_sig at `spics_out` array in each spi_periph.c of chips later than s2 then `spi_bus_add_device` can correctly distribute gpio_signals for cs_signal Closes https://github.com/espressif/esp-idf/issues/8876
98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/spi_periph.h"
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#include "stddef.h"
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/*
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Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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.spiclk_out = SPICLK_OUT_MUX_IDX,
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.spiclk_in = 0,/* SPI clock is not an input signal*/
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.spid_out = SPID_OUT_IDX,
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.spiq_out = SPIQ_OUT_IDX,
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.spiwp_out = SPIWP_OUT_IDX,
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.spihd_out = SPIHD_OUT_IDX,
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.spid_in = SPID_IN_IDX,
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.spiq_in = SPIQ_IN_IDX,
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.spiwp_in = SPIWP_IN_IDX,
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.spihd_in = SPIHD_IN_IDX,
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.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
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.spics_in = 0,/* SPI cs is not an input signal*/
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.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI1_INTR_SOURCE,
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.irq_dma = -1,
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.module = PERIPH_SPI_MODULE,
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.hw = (spi_dev_t *) &SPIMEM1,
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.func = SPI_FUNC_NUM,
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}, {
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.spiclk_out = FSPICLK_OUT_MUX_IDX,
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.spiclk_in = FSPICLK_IN_IDX,
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.spid_out = FSPID_OUT_IDX,
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.spiq_out = FSPIQ_OUT_IDX,
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.spiwp_out = FSPIWP_OUT_IDX,
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.spihd_out = FSPIHD_OUT_IDX,
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.spid4_out = FSPIIO4_OUT_IDX,
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.spid5_out = FSPIIO5_OUT_IDX,
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.spid6_out = FSPIIO6_OUT_IDX,
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.spid7_out = FSPIIO7_OUT_IDX,
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.spid_in = FSPID_IN_IDX,
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.spiq_in = FSPIQ_IN_IDX,
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.spiwp_in = FSPIWP_IN_IDX,
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.spihd_in = FSPIHD_IN_IDX,
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.spid4_in = FSPIIO4_IN_IDX,
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.spid5_in = FSPIIO5_IN_IDX,
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.spid6_in = FSPIIO6_IN_IDX,
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.spid7_in = FSPIIO7_IN_IDX,
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.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
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.spics_in = FSPICS0_IN_IDX,
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.spiclk_iomux_pin = FSPI_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = FSPI_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = FSPI_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = FSPI_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI2_INTR_SOURCE,
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.irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
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.module = PERIPH_FSPI_MODULE,
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.hw = &GPSPI2,
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.func = FSPI_FUNC_NUM,
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}, {
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.spiclk_out = SPI3_CLK_OUT_MUX_IDX,
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.spiclk_in = SPI3_CLK_IN_IDX,
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.spid_out = SPI3_D_OUT_IDX,
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.spiq_out = SPI3_Q_OUT_IDX,
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//SPI3 doesn't have wp and hd signals
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.spiwp_out = -1,
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.spihd_out = -1,
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.spid_in = SPI3_D_IN_IDX,
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.spiq_in = SPI3_Q_IN_IDX,
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.spiwp_in = -1,
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.spihd_in = -1,
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.spics_out = {SPI3_CS0_OUT_IDX, SPI3_CS1_OUT_IDX, SPI3_CS2_OUT_IDX},
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.spics_in = SPI3_CS0_IN_IDX,
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//SPI3 doesn't have iomux pins
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = ETS_SPI3_INTR_SOURCE,
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.irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
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.module = PERIPH_HSPI_MODULE,
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.hw = &GPSPI3,
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.func = -1,
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}
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};
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